Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 18 days ago

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Competitive pay

How this pay compares to similar roles

Similar $188k

This role $177k

$125k most similar roles pay here $235k

This role pays less than 52% of similar roles. Most pay $160,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Physical Design Engineer, Netlisting

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As a Senior ASIC Physical Design Engineer specializing in netlisting at NVIDIA, you will play a crucial role in the physical design of high-frequency and low-power CPUs, GPUs, SoCs across various levels. Your daily tasks include driving equivalence checking, asynchronous checks including clock domain crossing analysis, logic synthesis, and quality netlist assessments to ensure timing convergence and manage constraints effectively. You will work with industry-standard EDA tools for logic equivalence checking, FV, STA, and MTBF analysis, requiring expertise in scripting languages like Perl, TCL, Make, and Python. Ideal candidates have a background in electrical or computer engineering, hands-on experience in RTL/logic design, and a proven track record of improving workflows through AI integration.

Skills

Perl TCL Make Python RTL Logic Synthesis Equivalence Checking Clock Domain Crossing Checks MTBF Analysis Static Timing Analysis Timing Constraints Management EDA Tools DFT Timing Closure AI Utilization

What you'll do

Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at various levels with focus on netlist-related aspects.
Perform equivalence checking, asynchronous checks including clock domain crossing, and MTBF analysis for robust designs.
Generate and manage timing constraints to ensure effective timing convergence throughout the project.
Implement logic synthesis at block or full-chip level, contributing to both execution and flow development.
Utilize programming languages like Perl, TCL, Make, Python for scripting and automation in design processes.

What we're looking for

BS/MS in Electrical or Computer Engineering with 5+ years of relevant industry experience.
Expertise in logic equivalence checking/FV from RTL to tapeout using industry-standard tools.
Experience in clock-domain-crossing checks and MTBF analysis, either with standard or in-house tools.
Strong background in logic synthesis at block or full-chip level for timing closure.
Proficiency in Static Timing Analysis (STA), timing constraints management, and ECO implementation.
In-depth knowledge of industry-standard EDA tools and scripting languages like Perl, TCL, Python.

Hybrid

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