Senior Digital Design Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXRedmond, WA
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
146 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $183k
This role $177k
$126k $228k
below market most similar roles pay here above market

This role pays more than 56% of similar roles. Most pay $152,200–$214,000 — the blue band above. At the midpoint, this role pays about $177k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Digital Design Engineer

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The Senior Digital Design Engineer will join the Semi-Custom Silicon products group to develop NVLink Fusion based AI infrastructure System-on-Chips. This role involves analyzing architectural requirements, performing trade-off analyses, and delivering high-performance, area, and power-efficient RTL blocks. Key responsibilities include crafting micro-architecture specifications, implementing high-quality RTL, and ensuring blocks are synthesis and timing clean. The engineer will collaborate with architects, verification engineers, and SoC integration engineers while identifying and integrating specific IP solutions. Required expertise includes high-speed connectivity protocols like NVLink, PCI-Express, Ethernet, and UCIE. Candidates must demonstrate experience delivering high-bandwidth datapath blocks such as data movers, protocol adaptors, network-on-chip, arbiters, and schedulers. The position requires a deep understanding of ASIC design flows and methodology to solve rack-scale AI connectivity problems.

Skills

RTL ASIC Design NVLink PCI-Express Ethernet UCIE Network-on-Chip Micro-architecture Synthesis Data Movers Protocol Adaptors SoC Integration Formal Verification High-speed Connectivity AI Infrastructure

What you'll do

  • Analyze architectural requirements and perform trade-off analyses for hardware implementation.
  • Deliver high-performance, area-efficient, and power-efficient RTL blocks.
  • Craft detailed micro-architecture specifications for specific hardware blocks.
  • Implement high-quality RTL and deliver synthesis and timing-clean blocks.
  • Identify, select, customize, and integrate appropriate IP solutions for specific use cases.
  • Deliver high-bandwidth datapath blocks including data movers, protocol adaptors, and network-on-chip components.

What we're looking for

  • Bachelor's or Master's Degree in Electrical Engineering or Computer Engineering, or equivalent experience.
  • 5+ years of relevant work experience.
  • Experience working with high-speed connectivity protocols such as NVLink, PCI-Express, Ethernet, or UCIE.
  • Proven track record of delivering high bandwidth datapath blocks like data movers, protocol adaptors, network-on-chip, arbiters, and schedulers.
  • Deep understanding of ASIC design flows and methodology.
  • Strong analytical and interpersonal skills.

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