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Active Keyword: CPU Micro Remove filter Location: Santa Clara Remove filter Clear all

20 of up to 20 (filtered)

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 25 days ago $175,600–$263,400
Actively hiring Confirmed live today Trusted Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
4+ yrs exp
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CPU Micro-architect/RTL Designer

Qualcomm

Austin, TX +1 39 days ago $216,600–$325,000
Actively hiring Confirmed live today Low trust Above market
RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
8+ yrs exp
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CPU RTL/AI Micro-Architect

Qualcomm

Austin, TX +1 39 days ago $186,700–$280,100
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog SystemVerilog VHDL RTL Design LLM Agentic AI Simulation Waveform Debug Logic Design Synthesis CPU Architecture Microarchitecture Hardware Engineering
6+ yrs exp
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CPU Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Trusted Below market
RTL Verilog VHDL C C++ Python Perl Microarchitecture Formal Verification Simulation Emulation Out-of-Order Execution Branch Prediction
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CPU ML Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling
10+ yrs exp
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CPU ML Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling
3+ yrs exp
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CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Waveform Debugging
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling Load/Store Execution
3+ yrs exp
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Logic Design Waveform Debugging
3+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management Clock Generation Asynchronous Clock Crossing
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Design Coherence Protocols Interconnects Power Management
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management
3+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Design Coherence Protocols Interconnects Power Management
3+ yrs exp
Save

CPU Cache Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl Simulators Formal Methods DFT SRAM Coherence Protocols Interconnects Power Management
3+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog VHDL Microarchitecture CPU Cache C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects
10+ yrs exp
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CPU ML Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation Logic Design Out-of-Order Execution Instruction Scheduling Waveform Debugging
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Execution, Load/Store

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling Load/Store Execution
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live today Trusted Below market
RTL Verilog VHDL C C++ Python Perl Microarchitecture Formal Verification Simulation Emulation Out-of-Order Execution Branch Prediction
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CPU ML Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Memory Subsystems
3+ yrs exp
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