CPU Microarchitect/RTL Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$129,300–$194,700 / yr
Posted
16 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $215k
This role $162k
$112k most similar roles pay here $291k

This role pays less than 84% of similar roles. Most pay $180,075–$250,000 — the shaded band above. At the midpoint, this role pays about $162k versus about $215k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · CPU Microarchitect/RTL Engineer

The CPU Microarchitect/RTL Engineer joins the Silicon Engineering Group to drive multi-level cache subsystem architecture and RTL development for multi-processor systems. This role involves micro-architecture development from high-level exploration through detailed specification, as well as ownership of RTL design to meet power, performance, area, and timing goals. The engineer will perform performance exploration, support verification teams with test bench development and formal methods, and collaborate on physical design implementation. Required skills include proficiency in Verilog or VHDL, while preferred qualifications include experience in C, C++, Perl, or Python. Candidates may possess expertise in instruction fetch, branch prediction, out-of-order execution, load/store execution, or machine-learning hardware mapping. The role focuses on designing high-performance, low-power microprocessors to solve complex architectural challenges within the core processor domain.

What you'll do

  • Develop and specify micro-architecture from high-level exploration through detailed technical specifications.
  • Own RTL design by developing, assessing, and refining code to meet power, performance, area, and timing goals.
  • Support the verification team with test bench development, formal methods, and simulation/emulation.
  • Explore high-performance strategies and correlate results with performance verification teams.
  • Verify that the final RTL design meets all targeted performance metrics.
  • Collaborate with multi-functional teams to implement physical designs focusing on timing, area, reliability, and power.

What we're looking for

  • Minimum of a Bachelor's degree.
  • Experience with at least one of the following languages: Verilog or VHDL.
  • Expertise in areas such as instruction fetch, branch prediction, out-of-order execution, cache subsystems, or power management (preferred).
  • Understanding of low power microarchitecture techniques (preferred).
  • Understanding of high-performance techniques and trade-offs in a CPU microarchitecture (preferred).
  • Experience in C or C++ programming (preferred).
  • Experience using an interpretive language such as Perl or Python (preferred).

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