CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $184,700–$324,800 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $218k

This role $255k

$147k $344k

below market most similar roles pay here above market

This role pays more than 88% of similar roles. Most pay $181,000–$254,750 — the blue band above. At the midpoint, this role pays about $255k versus about $218k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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TL;DR · CPU Microarchitect/RTL Engineer, Fetch, Out of Order

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CPU Microarchitect/RTL Engineer - Fetch, Out of Order will join the Silicon Engineering Group to drive architecture and RTL development for performant CPU cores. This role involves owning micro-architecture development from high-level exploration to detailed specification, alongside RTL ownership to meet power, performance, area, and timing goals. Key responsibilities include supporting verification through test bench development and formal methods, performing performance exploration and correlation, and collaborating with multi-functional teams on physical design implementation. Candidates must possess experience in microprocessor architecture, logic design principles, Verilog or VHDL, and simulators for waveform debugging. Preferred skills include expertise in instruction fetch, decode, branch prediction, scheduling, register renaming, and out-of-order execution, as well as proficiency in C, C++, Perl, or Python for low power and high-performance CPU microarchitecture.

Skills

RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design

What you'll do

Develop and specify micro-architecture from high-level exploration to detailed technical specifications.
Own the development, assessment, and refinement of RTL design to meet power, performance, area, and timing goals.
Support the verification team in developing test benches, formal methods, and simulation or emulation for functional verification.
Explore high-performance strategies and correlate RTL design performance against targeted metrics.
Implement and verify physical design aspects including timing, area, reliability, testability, and power.
Drive architecture and RTL development for CPU front-end and out-of-order subsystems.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience with microprocessor architecture.
Experience with logic design principles with timing and power implications.
Experience in Verilog or VHDL.
Experience with simulators and waveform debugging process.
Expertise in instruction fetch and decode, branch prediction, instruction scheduling, register renaming, or out-of-order execution (preferred).
Understanding of low power microarchitecture techniques (preferred).
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture (preferred).
Experience in C or C++ programming (preferred).
Experience using an interpretive language such as Perl or Python (preferred).