CPU Cache Microarchitect RTL Engineer

What you'll do

• Develop and specify micro-architecture from high-level exploration through detailed technical specifications.
• Own the development, assessment, and refinement of RTL designs to meet power, performance, area, and timing goals.
• Support verification teams with test bench development, formal methods, and simulation or emulation for functional verification.
• Explore high-performance strategies and correlate results with performance verification teams to ensure targets are met.
• Implement and verify physical design aspects including timing, area, reliability, testability, and power.
• Design multi-level cache subsystems for high-performance, low-power multi-processor systems.

What we're looking for

• Minimum BS degree and 3+ years of relevant industry experience.
• Experience with microprocessor architecture.
• Experience with logic design principles involving timing and power implications.
• Experience in Verilog or VHDL.
• Experience with simulators and the waveform debugging process.
• Expertise in areas such as coherence protocols, interconnects, memory subsystem queuing, SRAM basics, or power management (preferred).
• Understanding of low power microarchitecture techniques and high-performance trade-offs (preferred).
• Experience in C/C++ or interpretive languages like Perl or Python (preferred).