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Python SystemVerilog UVM VCS Verdi Jenkins Make CI/CD Perl Docker Kubernetes Terraform AWS GCP Git GitHub Mercurial SVN Prometheus Grafana AI Machine_Learning +17 more Show less

Verilog SysVerilog C++ Python Perl TCL AgenticAI ClaudeCode Cursor CoPilot EDA ASIC Design for Testing Scan ATPG JTAG +11 more Show less

SystemVerilog UVM C++ Python Perl Formal Verification Coverage Metrics X-propagation DFT/IST Tegra GPU CI/CD +7 more Show less

Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence +9 more Show less

SystemVerilog UVM C++ Python PCIe CXL CHI VCS Debussy GDB +5 more Show less

UVM C/C++ Python Perl TCL SVA AXI APB DMA Memory Controllers QSPI UART I2C ASIC verification SoC verification UVM testbenches Constrained random methodology Assertion-based design checks Code coverage Functional coverage Formal test plan documentation AI tools +17 more Show less

SystemVerilog UVM Object-Oriented Programming Constrained Random Sequences Scoreboard Functional Coverage Memory Consistency Models Arbitration Policies Interface Protocols On-Chip Interconnect Caches xbar/Interconnect Fabric AI Tools Verification Methodologies +9 more Show less

SystemVerilog UVM Python Perl Design_Verification Logic_Design Logic_Synthesis CI/CD +3 more Show less

C++ SystemVerilog UVM VCS Debussy GDB Python CI/CD ASIC SoC GPU Verification methodology Random stimulus Functional coverage Assertion-based verification +10 more Show less

SystemVerilog UVM Perl Python Assertion-Based Verification Semiformal Verification Test Planning Coverage Closure Debugging Object Oriented Programming CI/CD +6 more Show less

SystemVerilog UVM VCS Verdi Indago GDB Perl C++ Python CI/CD +5 more Show less

SystemVerilog C++ UVM VCS Debussy GDB Python CI/CD Git Linux ASIC GPU Computer Architecture Digital Design Processor Pipeline Verification +10 more Show less

C++ SystemVerilog UVM Object-Oriented-Programming Python Perl Makefile Git CI/CD Linux Docker Jenkins SonarQube PostgreSQL SQLite VCS NC Verilog ModelSim GTKWave ASIC_Design_Knowledge +15 more Show less