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System Verilog UVM C/C++ VCS Verdi GDB Assertion-Based Verification Functional Coverage Random Stimulus ASIC Verification Processor Verification Instruction Pipelines Caches HVL +9 more Show less

System Verilog UVM VCS Verdi Indago GDB C/C++ Perl Assertion-Based Verification Functional Coverage Random Stimulus ASIC Verification Post-silicon Verification +8 more Show less

SystemVerilog UVM VCS RISCV C GDB Assertion-Based Verification Functional Coverage Random Stimulus SoC ASIC Verification Debussy Object Oriented Programming Memory Coherence High Speed IO Protocols +10 more Show less

SystemVerilog C++ UVM Verilog VHDL RTL ASIC Verification Computer Architecture SoC OOP Hardware Debug Logic Design HDL Simulation Functional Testing +10 more Show less

SystemVerilog UVM Python Perl Logic Design Logic Synthesis Design Verification DFT Clocking Structures Scripting +5 more Show less

System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Logic Design Coverage Metrics ASIC Design Verification Object-Oriented Programming Profiling Tools X prop +8 more Show less

System Verilog UVM C++ Python Perl ASIC Verification Formal Verification Constraint Random Verification Logic Design Coverage Metrics DFT IST Object-Oriented Programming X prop +9 more Show less

SystemVerilog UVM C++ VCS Digital Design Computer Architecture Assertion-Based Verification Functional Coverage Random Stimulus GDB Debussy Object-Oriented Programming Processor Pipeline Verification ASIC Verification +9 more Show less

SystemVerilog UVM VCS GDB C RISCV Assembly Assertion-based Verification Functional Coverage Random Stimulus SoC ASIC Verification Object Oriented Programming Debussy Embedded Microcontrollers +9 more Show less

SystemVerilog UVM ASIC Verification Computer Architecture RTL Assertion-Based Verification Object Oriented Programming Post-Silicon Validation Coverage Closure test bench design AI SFV +7 more Show less

SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS +10 more Show less

SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR SOC Cache post silicon debug PASIM Power Verification +8 more Show less

SystemVerilog UVM C++ Python Formal Verification assertion based verification UPF DDR SOC Cache post silicon debug PASIM Power Verification +8 more Show less

SystemVerilog UVM ASIC Verification VCS GDB RISCV C Firmware Object Oriented Programming Functional Coverage Assertion-Based Verification Memory Coherence High Speed IO Protocols Microcontrollers +9 more Show less

SystemVerilog UVM C C++ ASIC Verification Assertion-Based Verification Python Perl VCS IES GDB Debussy Functional Coverage Object Oriented Programming Memory Management Unit Computer Architecture Semiformal Verification (SFV +12 more Show less

UVM ASIC Verification C/C++ Python SVA AXI APB DMA Ethernet QSPI UART I2C Perl TCL Makefiles Perforce Code Coverage Functional Coverage +13 more Show less

ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis +10 more Show less

SystemVerilog C++ UVM VCS GDB Debussy Assertion-Based Verification Functional Coverage Random Stimulus ASIC Verification SoC GPU Memory Coherence High Speed IO Protocols Object Oriented Programming +10 more Show less

System Verilog UVM C C++ VCS Verdi GDB ASIC Verification Functional Coverage Assertion-Based Verification Random Stimulus GPU post silicon verification +8 more Show less

System Verilog UVM Verilog SVA VCS Questa Perl Tcl Make Formal Equivalence Gate Level Simulation LLMs Agentic AI Functional Coverage Mixed Signal Design Co-simulation ASIC Design Verification +12 more Show less