Senior ASIC Verification Engineer

Nvidia

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Quick summary

Work type
On-site
Location
Durham, NCHillsboro, ORMadison, ALSanta Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
55 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $216k
$129k $279k
below market most similar roles pay here above market

This role pays more than 76% of similar roles. Most pay $168,500–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

The Senior ASIC Verification Engineer joins the GPU ASIC Verification team to verify the Memory Management Unit. In this role, you will understand design implementation, define verification scope, and develop infrastructure including testbenches, BFMs, checkers, and monitors. You will implement test and coverage plans to verify design correctness while collaborating with architects, designers, and software engineers. Key responsibilities include planning the strategic direction of testbench methodology. Required skills include SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable components. You must understand constrained random testing, functional coverage, assertion-based verification, and object-oriented programming. Experience with VCS, IES, Debussy, and GDB is required. Preferred expertise includes UVM, memory subsystem micro-architecture, cache topologies, interconnects, arbiter designs, and scripting in Perl or Python.

What you'll do

  • Understand the design and implementation of the Memory Management unit.
  • Define the overall verification scope for the Memory Management unit.
  • Develop verification infrastructure including testbenches, BFMs, checkers, and monitors.
  • Implement comprehensive test and coverage plans to verify design correctness.
  • Plan and execute the strategic direction for advanced testbench methodologies.
  • Perform constrained random testing using functional coverage and assertion-based verification.
  • Create reusable verification components using SystemVerilog and object-oriented programming.
  • Debug and solve complex hardware issues using simulation and debug tools.

What we're looking for

  • Bachelor's or Master's Degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience.
  • 8+ years of relevant work or research experience.
  • Exposure to Computer Architecture, ASIC design, and verification methodology.
  • Strong ability with SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable verification components.
  • Knowledgeable in constrained random testing with functional coverage and assertion-based verification.
  • Understanding of object-oriented programming concepts.
  • Exposure to simulation tools like VCS, IES and debug tools like Debussy, GDB.
  • Understanding of memory subsystem micro-architecture, cache topologies, and interconnects (preferred).

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