ASIC Clocks Verification Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$116,000–$189,750 / yr
Employment
Full-time
Posted
2 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $153k
$104k $231k
below market most similar roles pay here above market

This role pays less than 71% of similar roles. Most pay $152,875–$216,250 — the blue band above. At the midpoint, this role pays about $153k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1472 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1109 roles with salary data.

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At a glance

TL;DR · ASIC Clocks Verification Engineer

The ASIC Clocks Verification Engineer - New College Grad 2026 joins the GPU clocks group to verify high frequency clock structures. This role involves collaborating with architects, ASIC designers, and verification engineers to design GPU clock structures that satisfy specific architectural constraints. You will deliver clock information to SOC verification, timing, and DFT teams while identifying improvements to current designs to overcome sub-micron design challenges. Daily tasks include debugging GPU clock silicon bugs with software and product groups and using Perl to improve team productivity. Required technical skills include SystemVerilog, Universal Verification Method (UVM), Logic Design, and Logic Synthesis. Candidates must demonstrate strong coding skills in Python or Perl. The work focuses on crafting all aspects of GPU clocking and defining efficient clock programming sequences.

What you'll do

  • Verify high-frequency clock structures using SystemVerilog and Universal Verification Method (UVM).
  • Design GPU clock structures that satisfy all architectural constraints and overcome sub-micron design challenges.
  • Deliver clock information to the SOC verification, timing, and DFT teams.
  • Use Perl to improve the productivity of various engineering teams.
  • Debug GPU clock silicon bugs in new products alongside the Software and product groups.
  • Identify and implement improvements to increase the efficiency of the GPU clocking design.
  • Provide clocking requirements and programming models to the front-end and software teams.

What we're looking for

  • Master’s degree in Electrical Engineering or equivalent experience.
  • Practical experience with SystemVerilog and Universal Verification Method (UVM).
  • Experience with Design Verification, Logic Design, and Logic Synthesis.
  • Strong coding skills in Python, Perl, or other industry-standard scripting languages.
  • Ability to verify high frequency clock structures and satisfy architectural constraints.
  • Ability to collaborate with multiple teams to debug silicon bugs and improve design efficiency.

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