ASIC Verification Engineer

Nvidia

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $100,000–$166,750 / yr
Employment: Full-time
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $181k

This role $133k

$86k $233k

below market most similar roles pay here above market

This role pays less than 84% of similar roles. Most pay $148,756–$214,000 — the blue band above. At the midpoint, this role pays about $133k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · ASIC Verification Engineer

Role Posting Log in to save

The ASIC Verification Engineer - New College Grad 2027 will join the team to support pre-silicon design verification activities ensuring proper hardware functionality. The primary responsibility involves simulating RTL under various conditions to identify design bugs early in the development process. Key tasks include employing AI technologies to create automated systems and flows, contributing to complex UVM testbench environments, and developing directed or random tests. The role requires verifying reference C++ and RTL models within a simulation environment while debugging RTL simulation failures. Candidates must demonstrate proficiency in SystemVerilog, C++, Verilog, and VHDL, alongside a solid understanding of OOP concepts and CPU or SoC architecture. This position focuses on hardware debug and functional testing for GPU or processor verification within a complex hardware design context.

Skills

SystemVerilog C++ UVM Verilog VHDL RTL ASIC Verification Computer Architecture SoC OOP Hardware Debug Logic Design HDL Simulation Functional Testing

What you'll do

Simulate RTL under various conditions to identify and resolve design bugs early in the pre-silicon process.
Employ cutting-edge AI technologies to create automated systems and verification flows.
Contribute to complex UVM testbench environments including test development, automation, and analysis.
Develop directed and random tests in SystemVerilog to verify reference C++ and RTL models.
Debug RTL simulation failures to ensure proper hardware functionality.
Write test plans and perform random diagnostics for hardware verification.

What we're looking for

Pursuing or recently completed a BS, MS, or PhD in EE, CE, or a related field.
Coursework or prior internship exposure to computer architecture, logic design, and HDL languages like Verilog or VHDL.
Strong programming experience in C++ or SystemVerilog and a general understanding of OOP concepts.
Solid understanding of basic concepts of CPU or SoC architecture.
Exceptional analytical and problem-solving skills.
Experience with HW/SW interactions (preferred).
Experience with directed and random functional testing, including writing test plans and diagnostics (preferred).
Internship or lab experience with GPU or Processor verification, validation, or hardware debug (preferred).

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