Senior ASIC Verification Engineer

Nvidia

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 22 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$126k most similar roles pay here $230k

This role pays less than 53% of similar roles. Most pay $168,500–$216,062 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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As a Senior ASIC Verification Engineer, you will join the ASIC Verification team to ensure the integrity of leading SoCs and GPUs for automotive and gaming console applications. You will be responsible for verifying the design, architecture, golden models, and micro-architecture of ARM based System on-chip backbone IPs to ensure first-pass silicon success. Your daily work involves defining verification scopes, developing robust infrastructure, and integrating AI and LLM-driven workflows into the cycle. You will utilize UVM, C/C++, Python, Perl, or TCL to build testbenches from scratch and automate flows. Key technical areas include SVA, code coverage, functional coverage, and expertise in Low-Speed IOs like QSPI, UART, I2C, High-Speed Ethernet, AXI/APB interconnects, DMA controllers, and Memory Controllers. You will collaborate with architects and designers to resolve complex SoC-level corner cases.

Skills

UVM ASIC Verification SVA C++ C Python Perl TCL ARM SoC Ethernet AXI APB DMA Memory Controllers Makefiles Perforce

What you'll do

Verify the design and implementation of high-performance SoCs to ensure first-pass silicon success.
Lead verification of ASIC designs, architectures, golden models, and micro-architecture using UVM methodologies.
Develop robust verification infrastructure to verify the correctness of complex logic.
Integrate AI and LLM-driven workflows into the verification cycle to optimize testbench generation and debug productivity.
Build UVM testbenches from scratch using constrained random methodology in a production environment.
Develop architectural golden models and hardware-software co-verification tests using C/C++.
Perform assertion-based design checks, code coverage analysis, and functional coverage tracking.
Automate build flows and regressions using Python, Perl, or TCL scripting.

What we're looking for

BS degree in Electrical Engineering, Computer Engineering, or Computer Science; MS or PhD degrees are preferred.
5+ years of experience in ASIC verification-related fields at both the IP and SoC level.
Proven experience building UVM testbenches from scratch and applying constrained random methodology in a production environment.
High proficiency in C/C++ to develop architectural golden models and hardware-software co-verification tests.
Deep domain knowledge of Low-Speed IOs, High-Speed IOs (Ethernet), AXI/APB interconnects, DMA controllers, and Memory Controllers.
Expert skills in assertion-based design checks (SVA), code coverage, functional coverage, and formal test plan documentation.
Professional-grade scripting abilities in Python, Perl, or TCL to automate build flows and regressions.
Advanced UVM architecture knowledge and large-scale SoC verification experience are preferred.

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