Senior ASIC Verification Engineer

Nvidia

Confirmed live today Low trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 68 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$125k $236k

below market most similar roles pay here above market

This role pays less than 56% of similar roles. Most pay $168,500–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

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The Senior ASIC Verification Engineer joins a global team focused on the micro-architecture, design, verification, implementation, and post-silicon validation of automotive and gaming console chips. This role involves verifying the design and implementation of industry-leading SoCs, specifically focusing on backbone IPs for an ARM-based System on-chip. You will lead verification of ASIC designs, architectures, golden models, and micro-architectures using UVM methodologies. Responsibilities include defining verification scope, developing robust infrastructure for complex logic, and collaborating with architects and designers to drive coverage. You will utilize C/C++, Python, Perl, and TCL to build testbenches and automate flows. Required expertise includes SVA, constrained random methodology, and domain knowledge in Low-Speed IOs, High-Speed Ethernet, AXI/APB interconnects, DMA controllers, and Memory Controllers.

Skills

UVM ASIC Verification C/C++ Python SVA AXI APB DMA Ethernet QSPI UART I2C Perl TCL Makefiles Perforce Code Coverage Functional Coverage

What you'll do

Lead the verification of ASIC designs, architectures, golden models, and micro-architectures using UVM methodologies.
Develop robust verification infrastructure to ensure the correctness of complex logic.
Define the verification scope and drive comprehensive coverage for SoC designs.
Integrate AI and LLM-driven workflows to optimize testbench generation and debug productivity.
Build UVM testbenches from scratch using constrained random methodology in production environments.
Develop architectural golden models and hardware-software co-verification tests using C/C++.
Perform assertion-based design checks, code coverage analysis, and functional coverage tracking.
Automate build flows and regressions using Python, Perl, or TCL scripting.

What we're looking for

BS or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
MS or PhD degrees are a plus (preferred).
5+ years of experience in ASIC verification-related fields at both the IP and SoC level.
Proven experience building UVM testbenches from scratch and applying constrained random methodology in production.
High proficiency in C/C++ to develop architectural golden models and hardware-software co-verification tests.
Deep domain knowledge in Low-Speed IOs, High-Speed IOs, AXI/APB interconnects, DMA controllers, and Memory Controllers.
Expert skills in assertion-based design checks (SVA), code coverage, functional coverage, and formal test plan documentation.
Professional-grade scripting abilities in Python, Perl, or TCL to automate build flows and regressions.

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