ASIC Verification Engineer

Nvidia

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $116,000–$189,750 / yr
Posted: 9 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k

This role $153k

$103k most similar roles pay here $236k

This role pays less than 81% of similar roles. Most pay $162,000–$214,000 — the shaded band above. At the midpoint, this role pays about $153k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · ASIC Verification Engineer

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The ASIC Verification Engineer joins the Clocks team to deliver high-quality clocking and reset logic for various units in SOC and GPU ASIC products. This role involves owning the validation of clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, coverage metrics, and bug identification. The engineer will tackle sophisticated problems by developing scalable solutions across platforms while partnering with architecture and design teams. Key responsibilities include utilizing industry-standard tools and methodologies such as SV constraint random verification, UVM, Formal Verification, and profiling tools. Required technical skills include proficiency in System Verilog, C++, Perl, Python, and custom compilers. The role addresses the increasing complexity of clocking and reset designs to ensure bug-free performance across data centers, consumer graphics, self-driving cars, and artificial intelligence applications.

Skills

System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Logic Design Coverage Metrics Object-Oriented Programming Automation Scripting ASIC Design Verification

What you'll do

Own the end-to-end validation of clocking structures for Tegra and GPU products.
Develop comprehensive test plans, automation scripts, and verification flows for complex designs.
Implement and manage coverage metrics to ensure high-quality, bug-free clock and reset logic.
Solve sophisticated technical problems by developing scalable verification solutions across multiple platforms.
Write production-level code using SystemVerilog, UVM, C++, Perl, and Python.
Utilize formal verification and constraint-random methodologies to validate block and system-level designs.
Develop reusable verification methodologies and tools for use by other engineering teams.

What we're looking for

BS or MS in EE/ECE or equivalent experience.
3+ years of proven design verification experience.
Good understanding of Logic Design and Architecture.
Expertise in SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, and X prop.
Strong coding skills in SystemVerilog, C++, and scripting languages like Perl or Python.
Experience with block-level and system-level verification.
Experience implementing test plans for pre-silicon platforms.
Ability to collaborate with multiple groups and drive projects to completion.

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