ASIC Verification Engineer

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$116,000–$189,750 / yr
Employment
Full-time
Posted
22 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k
This role $153k
$103k $238k
below market most similar roles pay here above market

This role pays less than 83% of similar roles. Most pay $162,000–$216,250 — the blue band above. At the midpoint, this role pays about $153k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · ASIC Verification Engineer

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The ASIC Verification Engineer joins the Clocks team to deliver high-quality clocking and reset logic for SOC and GPU ASIC products. This role involves owning the validation of clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows, coverage metrics, and bug identification. The engineer must develop scalable solutions for complex design specifications while balancing infrastructure constraints and multi-platform support. Key responsibilities include coding in SystemVerilog, UVM, C++, Perl, and Python using industry-standard tools and formal verification methodologies. The position requires expertise in logic design, architecture, and constraint random verification to solve sophisticated problems within the clocking and reset design space for data centers, consumer graphics, self-driving cars, and artificial intelligence.

Skills

System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Logic Design Coverage Metrics ASIC Design Verification Object-Oriented Programming Profiling Tools X prop

What you'll do

  • Own the end-to-end validation of clocking structures for Tegra and GPU products.
  • Develop comprehensive test plans, automation flows, and coverage metrics for clocking designs.
  • Execute tests to identify, track, and fix bugs within the clocking and reset logic.
  • Code verification environments using SystemVerilog, UVM, C++, Perl, and Python.
  • Develop scalable verification solutions that work across multiple hardware platforms.
  • Implement industry-standard verification methodologies including constraint random verification and formal verification.
  • Productize verification flows to ensure high-quality, bug-free designs for production.

What we're looking for

  • BS or MS in EE/ECE or equivalent experience.
  • 3+ years of proven design verification experience.
  • Good understanding of Logic Design and Architecture.
  • Expertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, and coverage metrics.
  • Strong coding skills in System Verilog, C++, and scripting languages like Perl and Python.
  • Experience in implementing test plans for pre-silicon platforms.
  • Previous experience automating tasks in the design verification process (preferred).
  • Hands-on experience in object-oriented programming (preferred).

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