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ASIC SoC Physical Design RTL-to-GDSII Floorplanning STA IR/EM PV TCL Python Shell PnR CTS MMMC ECO SDC Mixed-Signal DFT +13 more Show less

Networking Security Cloud AI Infrastructure Routing Switching Wireless VPN Zero Trust Firewall High-Performance Fabrics Hybrid Cloud Telemetry Observability Lab Validation Performance Testing Interoperability Testing +12 more Show less

ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation +12 more Show less

ASIC Package Design Signal Integrity (SI) Power Integrity (PI) High-Speed Routing Power Distribution Networks (PDN) EDA Tools Python Perl TCL Shell Programming Oscilloscopes TDR VNA Silicon Floor Planning Tapeout Hardware Development +11 more Show less

ASIC Signal Integrity Power Integrity SerDes SPICE Keysight ADS Ansys HFSS Cadence APD Python MATLAB IBIS Vector Network Analysis HBM UCIe CoWoS EMIB Transmission Line Theory Electromagnetics +13 more Show less

C C++ Python Linux SONiC Device Driver Development I2C PCIe SPI MDIO TCP/IP Layer 2 Layer 3 ASIC Hardware Bring-up Secure-boot SFP QSFP +13 more Show less

Go Python Kubernetes Distributed Systems Microservices OAuth 2.0 OIDC JWT mTLS gRPC Protobuf Kafka PostgreSQL Weaviate Milvus Qdrant OpenTelemetry Temporal LaunchDarkly SSE WebSockets zero-trust +17 more Show less

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug RTL +11 more Show less

AI-Native Software Engineering Security Engineering MCP Servers Threat Intelligence Compliance Governance Automation +2 more Show less

Saviynt Microsoft Entra ID Azure AD B2C Cisco Duo Astrix Security Identity and Access Management (IAM) REST APIs PowerShell SAML 2.0 OAuth 2.0 OpenID Connect (OIDC) Active Directory Microsoft 365 SAP Salesforce Informatica Zero Trust Workflow Automation +13 more Show less

DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation ATE P1687 RTL Physical Design +15 more Show less

Python Cisco IOS-XR Linux SONiC FBOSS VXLAN MACsec gNMI OpenConfig YANG Ixia Spirent AI ML LLM Telemetry Routing Switching +13 more Show less

Fiber Optics Optical Transceivers Switching Routing Interoperability Testing System Functional Validation IEEE 802.3xx Optical MSAs SFF QSFP-DD CMIS Optical Spectrum Analyzers High-speed Scopes AI Datacenter Networks Product Requirement Documents Validation Test Plans +11 more Show less

ASIC DFT Post-Silicon Validation Verilog VCS Gate Level Simulation ATE Patterns P1687 Static Timing Analysis DFT CAD Hardware Bring-up IP Integration Test Architecture Methodology Infrastructure +10 more Show less

System Verilog UVM DFT Python TCL Perl Verdi JTAG MBIST Scan Architecture Boundary Scan ATE RTL Physical Design post silicon validation +10 more Show less

ASIC RTL CDC RDC SDC VCS SVA SystemVerilog Synthesis Gate Netlists +5 more Show less

DFT CAD Python Tcl Perl Shell Scripting LSF Synopsys TestMAX Synopsys VCS Siemen's Tessent AI ML Pandas STIL ATPG RTL SoC Integration +12 more Show less

C C++ Linux DPDK P4 Data Plane Packet Processing Layer 2 Layer 3 Networking Protocols SmartNICs Network Processors Systems Programming Software Development Lifecycle Debugging Performance Optimization +11 more Show less

ASIC FPGA Verilog HDL VHDL Python Tcl PCIe I2C SPI Ethernet Schematic Capture Hardware Bring-up Signal Integrity DFT DRAM CPU Analyzers +12 more Show less

Networking Security Cloud AI Infrastructure Routing Switching Wireless VPN Zero Trust Firewall Hybrid Cloud Telemetry Observability Performance Testing Interoperability Testing Automation Data Center Architecture +12 more Show less