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Active Keyword: Silicon Engineering Remove filter Location: Irvine Remove filter Clear all

16 of up to 20 (filtered)

New Graduate Engineer, Silicon Engineering

SpaceX

Palo Alto, CA +2 29 days ago $135,000–$175,000
Actively hiring Confirmed live 2 days ago High trust Below market
ASIC FPGA RTL Design SystemVerilog Verilog VHDL C C++ Python RFIC MMIC DSP MATLAB ADS Spectre HFSS Momentum CMOS Physical Design tapeout
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New Graduate Engineer, Silicon Engineering

SpaceX

Palo Alto, CA +2 29 days ago $125,000–$165,000
Actively hiring Confirmed live 2 days ago High trust Below market
ASIC FPGA RTL Design SystemVerilog Verilog VHDL C C++ Python RFIC MMIC DSP MATLAB ADS Spectre HFSS Momentum CMOS Physical Design tapeout
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New Graduate Engineer, Silicon Engineering

SpaceX

Palo Alto, CA +2 29 days ago $125,000–$160,000
Actively hiring Confirmed live yesterday High trust Below market
ASIC FPGA RTL Design SystemVerilog Verilog VHDL C++ Python RFIC MMIC DSP MATLAB ADS Spectre HFSS Momentum CMOS Physical Design Synthesis tapeout
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Senior DSP Systems Engineer, Silicon Engineering

SpaceX

Irvine, CA 30 days ago $165,000–$265,000
Actively hiring Confirmed live yesterday Trusted Above market
Digital Signal Processing ASIC FPGA MATLAB Python C++ GNU Radio Multi-access Schemes Link Budgets Beamforming Massive MIMO Git JIRA Confluence Bitbucket Bamboo
5+ yrs exp
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Silicon Engineering Internship/Co-op

SpaceX

Irvine, CA +2 40 days ago
Actively hiring Confirmed live yesterday Trusted
VLSI Design Logic Design Circuit Design C++ Verilog VHDL Python Perl Spice Timing Synthesis Ansys COMSOL Formal Methods Verification Computer Architecture ASIC Implementation
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Silicon Engineering Internship

SpaceX

Irvine, CA +5 40 days ago
Actively hiring Confirmed live 2 days ago Trusted
VLSI Design Logic Design Circuit Design Computer Architecture Verilog VHDL C++ C Python Perl Spice Timing Synthesis Ansys COMSOL Formal Methods Verification
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Principal DFT Engineer

SpaceX

Irvine, CA 44 days ago $210,000–$340,000
Actively hiring Confirmed live 2 days ago Trusted Above market
DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog RTL Python Perl Tcl UPF Formal Verification Gate Level Simulation SDF ATE DRC
10+ yrs exp
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Design Verification Engineer, Silicon Engineering

SpaceX

Irvine, CA 60 days ago $125,000–$145,000
Actively hiring Confirmed live 2 days ago Low trust Below market
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 60 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage
5+ yrs exp
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Senior Technical Project Lead, Silicon Engineering

SpaceX

Irvine, CA 78 days ago $165,000–$260,000
Actively hiring Confirmed live 2 days ago Low trust Competitive pay
ASIC Silicon Design Tape-out FPGA ATE Testing Firmware RF Jira Smartsheet Confluence Project Management Product Lifecycle
8+ yrs exp
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Senior Full Chip Physical Verification Engineer

SpaceX

Irvine, CA 106 days ago $165,000–$260,000
Actively hiring Confirmed live 2 days ago Low trust Above market
DRC LVS PERC ESD Calibre ICV Pegasus ASIC Physical Design Python TCL Perl Bash Makefile SoC DFT tapeout Advanced Nodes Rule Deck Validation
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA 109 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis
5+ yrs exp
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Senior RTL Design Engineer

SpaceX

Irvine, CA 114 days ago $165,000–$260,000
Actively hiring Confirmed live 3 days ago Low trust Competitive pay
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators EDA Tools Clock Domain Crossing Power Optimization Silicon Bring-up
5+ yrs exp
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Principal Design Verification Engineer

SpaceX

Irvine, CA 114 days ago $210,000–$335,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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Physical Design Engineer II, Silicon Engineering

SpaceX

Irvine, CA 151 days ago $145,000–$195,000
Actively hiring Confirmed live yesterday Low trust Below market
ASIC RTL2GDSII Physical Design STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis
3+ yrs exp
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RTL Design Engineer, Silicon Engineering

SpaceX

Irvine, CA 179 days ago $125,000–$145,000
Actively hiring Confirmed live 2 days ago Low trust Below market
RTL Design SystemVerilog Verilog VHDL ASIC FPGA Python DSP AXI AHB APB EDA Tools HDL Simulators
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