This role pays less than
87%
of similar roles. Most pay
$161,375–$227,350
— the shaded band above.
At the midpoint, this role pays about
$145k
versus about
$194k
for comparable roles.
Based on 240 similar postings.
Employer
About SpaceX
SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.
SpaceX currently has
680 open roles
on FindRole.
Listed pay typically runs
$130,000–$165,000
across 442 roles with salary data.
New Graduate Engineer, Silicon Engineering will join the team developing next-generation silicon for the Starlink program. This role involves participating in all phases of ASIC and FPGA design and verification flows, including architecture, RTL implementation, and emulation. The engineer will perform chip bring-up and validation in the lab using C/C++ or Python, while also contributing to RF/Analog IC design, modeling systems at a high level, and performing floor planning and layout for SiGe or CMOS processes. Key responsibilities include developing RTL designs with SystemVerilog for digital signal processing blocks and executing physical design steps like synthesis, place and route, and timing analysis. Required skills include experience with ASIC, SOC, FPGA, or RFIC technologies, along with proficiency in Verilog, VHDL, Python scripting, and simulation tools such as ADS, Spectre, HFSS, or Momentum.
What does a Engineer earn in California?
Median $208000 from 94 postings across 22 companies.
Execute all phases of ASIC and FPGA design, including architecture, RTL implementation, and verification.
Bring up and validate ASICs and FPGAs in the lab using C/C++ or Python.
Simulate and model RFIC systems to partition functions between hardware and software domains.
Develop RF and microwave circuits using state-of-the-art SiGe or CMOS processes.
Create RTL designs for DSP and digital communication system blocks using SystemVerilog.
Perform physical design steps including synthesis, floor planning, place and route, and timing analysis.
Develop and improve automation scripts for various physical design implementation steps.
Participate in silicon tapeouts for advanced technology nodes to support Starlink SOCs.
What we're looking for
Must be graduating with a bachelor's degree, master's degree, or PhD in 2026 or 2027.
Degree must be in an engineering discipline, mathematics, or physics.
Experience working with ASIC, SOC, FPGA, RFIC, or MMIC.
Understanding of computer architecture (preferred).
Experience in analog or digital CMOS integrated circuit design and/or physical design (preferred).
Proficiency in SystemVerilog, Verilog, VHDL, or C/C++ (preferred).
Experience with scripting languages like Python for automation, object-oriented programming, or simulation tools such as ADS, Spectre, HFSS, or Momentum (preferred).
Must be a U.S. citizen, national, lawful permanent resident, or eligible for required export control authorizations.