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FPGA SoC Chiplet RTL Partial Reconfiguration Bitstream Silicon Architecture Memory Hierarchy High-Speed Interconnects Synthesis Place-and-Route System Integration Debug Observability +8 more Show less

UVM System Verilog C-DPI FPGA ASIC Firmware SoC AXI AHB DMA Cryptography Data Compression Silicon Bring-up Emulation Micro-architecture +10 more Show less

SoC VLSI ASIC Python JavaScript Perl LLM Claude Code JIRA Confluence Project Management Bug Tracking Pre-silicon Prototyping +8 more Show less

SoC VLSI ASIC Python JavaScript Perl LLM Claude Code JIRA Confluence Project Management Bug Tracking Pre-silicon Prototyping +8 more Show less

ASIC FPGA RTL Design SystemVerilog Verilog VHDL C C++ Python RFIC MMIC DSP MATLAB ADS Spectre HFSS Momentum CMOS Physical Design tapeout +15 more Show less

ASIC FPGA RTL Design SystemVerilog Verilog VHDL C C++ Python RFIC MMIC DSP MATLAB ADS Spectre HFSS Momentum CMOS Physical Design tapeout +15 more Show less

ASIC FPGA RTL Design SystemVerilog Verilog VHDL C++ Python RFIC MMIC DSP MATLAB ADS Spectre HFSS Momentum CMOS Physical Design Synthesis tapeout +15 more Show less

Digital Signal Processing ASIC FPGA MATLAB Python C++ GNU Radio Multi-access Schemes Link Budgets Beamforming Massive MIMO Git JIRA Confluence Bitbucket Bamboo +11 more Show less

Digital Signal Processing ASIC FPGA MATLAB Python C++ GNU Radio Massive MIMO Beamforming Link Budgets Modem Design LTE WiFi Git JIRA Confluence Bitbucket Bamboo +13 more Show less

ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF RTL Physical Design Formal Verification DRC Synthesis Silicon Engineering +13 more Show less

ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF DRC Formal Verification RTL Physical Design +11 more Show less

VLSI Design Logic Design Circuit Design C++ Verilog VHDL Python Perl Spice Timing Synthesis Ansys COMSOL Formal Methods Verification Computer Architecture ASIC Implementation +12 more Show less

VLSI Design Logic Design Circuit Design Computer Architecture Verilog VHDL C++ C Python Perl Spice Timing Synthesis Ansys COMSOL Formal Methods Verification +12 more Show less

DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog Python Perl Tcl RTL UPF Gate Level Simulation SDF Formal Verification ATE +12 more Show less

DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog RTL Python Perl Tcl UPF Formal Verification Gate Level Simulation SDF ATE DRC +13 more Show less

DFT ASIC Siemens Tessent ATPG Scan Insertion BIST Verilog SystemVerilog RTL Python Perl Tcl UPF Formal Verification Gate Level Simulation SDF ATE +12 more Show less

SoC ARM v8 Python C++ Power Analysis Performance Analysis Benchmarking SMMU GIC CoreSight-PMU Data Center Workloads Logic Analyzers Oscilloscopes Scripting System Architecture +10 more Show less

SoC Silicon Bring-up FPGA Prototyping Wireless Connectivity Standards System Validation Bug Tracking Project Management Risk Management Test Engineering Pre-silicon Development +5 more Show less

SoC Silicon Bring-up FPGA Prototyping Wireless Connectivity Standards System Validation Bug Tracking Project Management Risk Management Technical Program Management +4 more Show less

Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ CPO mixed signal DSP CTLE +10 more Show less