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20 of up to 20 (filtered)

Senior IC Package Design Engineer

SpaceX

Irvine, CA +1 4 days ago $165,000–$265,000
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
IC Package Design ASIC RFIC Power Integrity EM Simulation Cadence APD+ SIP HFSS SIWave ADS BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal silicon floor plan
5+ yrs exp

Senior IC Package Design Engineer

SpaceX

Austin, TX +1 4 days ago
Actively hiring Confirmed live yesterday Posted this week Trusted
IC Package Design ASIC RFIC Cadence APD+ SIP SIWave HFSS ADS Power Integrity EM Simulation BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal
5+ yrs exp

SoC Pre-Silicon Platform Engineering Program Manager

Apple Inc

Cupertino, CA 12 days ago $144,600–$263,800
Actively hiring Confirmed live yesterday High trust Competitive pay
SoC FPGA Emulation Simulation Virtual Platforms Firmware Silicon Bring-up Platform Architecture Validation Pre-silicon Modeling
3+ yrs exp

Silicon Photonics Design Engineer

SpaceX

Palo Alto, CA +1 12 days ago $135,000–$175,000
Actively hiring Confirmed live today Trusted Below market
Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ MZM Microring Modulators InGaAs InP CTLE Spectrum Analyzers Vector Signal Analyzers High Speed Oscilloscopes BERT Floor Planning
2+ yrs exp

Senior Silicon Photonics Design Engineer, RFIC Engineering

SpaceX

Palo Alto, CA +1 12 days ago $175,000–$280,000
Actively hiring Confirmed live today Trusted Above market
Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ MZM Microring Modulators InGaAs InP CTLE Spectrum Analyzers Vector Signal Analyzers High Speed Oscilloscopes BERT Floor Planning
5+ yrs exp

Senior ASIC Design Engineer

SpaceX

Palo Alto, CA +3 18 days ago $175,000–$280,000
Actively hiring Confirmed live today Trusted Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp

ASIC Design Engineer

SpaceX

Palo Alto, CA +2 18 days ago $135,000–$175,000
Actively hiring Confirmed live today Trusted Below market
ASIC Design FPGA Verilog SystemVerilog VHDL RTL Design Python C/C++ Bash SoC Integration DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer

Senior RF Silicon Software Engineer

SpaceX

Redmond, WA 26 days ago $165,000–$270,000
Actively hiring Confirmed live today Trusted Above market
C C++ Python Embedded Software RFIC FPGA SystemVerilog Hardware-in-the-loop HIL Logic Analyzers Oscilloscopes Unit Testing Performance Optimization Register Access PCB Layout Schematics
5+ yrs exp

Senior ASIC Design Engineer

SpaceX

Irvine, CA +3 27 days ago $165,000–$265,000
Actively hiring Confirmed live today Trusted Competitive pay
Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp

FPGA/ASIC Design Engineer

SpaceX

Irvine, CA +1 27 days ago $125,000–$160,000
Actively hiring Confirmed live today Trusted Below market
ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer SoC Integration

RF Silicon Software Engineer

SpaceX

Redmond, WA 27 days ago $125,000–$165,000
Actively hiring Confirmed live today Trusted Below market
C C++ Python Embedded Software FPGA SystemVerilog Hardware-in-the-loop HIL RF Communication Systems Logic Analyzers Oscilloscopes PCB Layout Register Access Unit Testing Performance Optimization
1+ yrs exp

Senior ASIC Design Engineer

SpaceX

Redmond, WA +3 27 days ago $165,000–$270,000
Actively hiring Confirmed live today Trusted Above market
RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems
5+ yrs exp

Senior ASIC Design Engineer

SpaceX

Austin, TX +3 27 days ago
Actively hiring Confirmed live today Low trust
Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up
5+ yrs exp

FPGA/ASIC Design Engineer

SpaceX

Redmond, WA +1 27 days ago $125,000–$165,000
Actively hiring Confirmed live today Trusted Below market
ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer

CPU Pre-Silicon Engineering Program Manager

Apple Inc

Cupertino, CA 40 days ago $175,500–$311,700
Actively hiring Confirmed live today High trust Above market
CPU Architecture Logic Design Verification Physical Design DFT SoC Silicon Validation Tapeout Project Management Program Management
10+ yrs exp

CPU Pre-Silicon Engineering Program Manager

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today High trust
CPU Architecture Logic Design Verification Physical Design DFT SoC Silicon Validation Tapeout Project Management Program Management Technical Leadership
10+ yrs exp

Physical Design Engineer

SpaceX

Palo Alto, CA +2 46 days ago $135,000–$175,000
Actively hiring Confirmed live today Low trust Below market
ASIC Design RTL2GDSII Physical Design Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
1+ yrs exp

Physical Design Engineer

SpaceX

Austin, TX +2 46 days ago
Actively hiring Confirmed live today Low trust
ASIC Design RTL2GDSII Physical Design Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python Perl TCL Bash Makefile EDA Tools
1+ yrs exp

Physical Design Engineer

SpaceX

Irvine, CA +2 46 days ago $125,000–$160,000
Actively hiring Confirmed live today Low trust Below market
ASIC Design RTL2GDSII Physical Design Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools
1+ yrs exp