Sr. RTL Design Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $160,000–$225,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $181k

This role $192k

$144k most similar roles pay here $234k

This role pays more than 60% of similar roles. Most pay $154,525–$208,225 — the shaded band above. At the midpoint, this role pays about $192k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. RTL Design Engineer (Silicon Engineering)

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Senior RTL Implementation Engineer position available in Irvine, CA for a leading semiconductor company. This role involves providing timing constraints for IPs and supporting the physical implementation team with synthesis, timing closure, and formality checks. The ideal candidate will have 5+ years of experience in RTL implementation, familiarity with ASIC/SoC system integration, and expertise in embedded CPU subsystems including AXI and AHB protocols. Strong scripting skills (Python) and proficiency with EDA tools such as HDL simulators and linting utilities are essential. This role requires a deep understanding of hardware design challenges at scale within the semiconductor industry.

Skills

Python EDA tools HDL simulators HDL Lint tools AXI AHB RF Verification Mentor Graphics Calibre RISC-V

What you'll do

Provide timing constraints for IPs during the design process.
Support physical implementation teams with synthesis and timing closure tasks.
Conduct formality checks to ensure design integrity.
Utilize EDA tools such as HDL simulators and linting tools effectively.
Script in Python or other languages to automate design processes.

What we're looking for

5+ years of experience in RTL implementation
Experience with ASIC/SoC system integration and embedded CPU subsystems
Proficiency in scripting languages like Python
Expertise with EDA tools including HDL simulators and linting tools
Knowledge of bus protocols such as AXI, AHB

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