Physical Design Engineer II, Silicon Engineering

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$145,000–$195,000 / yr
Posted
150 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k
This role $170k
$135k most similar roles pay here $240k

This role pays less than 68% of similar roles. Most pay $154,525–$219,043 — the shaded band above. At the midpoint, this role pays about $170k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer II, Silicon Engineering

Role Posting Log in to save

As a Physical Design Engineer II (Silicon Engineering), you will join a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. You will perform critical physical implementation steps including partition synthesis, floorplanning, power/ground grid generation, place and route, and various signoff checks such as static timing analysis, noise, electromigration, and voltage drop. Additionally, you will develop automation scripts and improve design methodologies while collaborating with the ASIC team on architectural feasibility and RTL tradeoffs. The role requires expertise in RTL2GDSII flows, deep sub-micron FinFET and CMOS solid state physics, and standard cell libraries. You will utilize industry-standard EDA tools and scripting languages like Python, Perl, TCL, and Bash to resolve congestion issues. This position focuses on the technical challenge of building hardware that enables global connectivity through the Starlink network.

Skills

ASIC RTL2GDSII Physical Design STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, power/ground grid generation, and place and route.
  • Execute signoff checks for timing, noise, physical verification, electromigration, voltage drop, and logic equivalency.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies with the ASIC design team to establish timing, power, and area targets.
  • Resolve complex design, timing, and congestion issues while identifying and driving technical solutions.
  • Run, debug, and fix signoff closure issues in static timing analysis and physical verification flows.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 3+ years of professional experience in RTL2GDSII physical design and/or physical design flow development.
  • Experience with industry standard EDA tools and understanding of their capabilities and algorithms.
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics.
  • Understanding of CMOS digital design principles, standard cell functionality, and power dissipation in deep submicron processes.
  • Familiarity with CMOS analog circuit and physical design.
  • Basic knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows.
  • Proficiency in scripting languages such as csh, bash, Perl, Python, TCL, or Makefile.

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