Physical Design Engineer II (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $145,000–$175,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $174k

This role $160k

$131k most similar roles pay here $222k

This role pays less than 63% of similar roles. Most pay $144,500–$202,850 — the shaded band above. At the midpoint, this role pays about $160k versus about $174k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer II (Silicon Engineering)

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The Physical Design Engineer II role at Silicon Engineering in Irvine, CA is a mid-level position within the semiconductor design team. This engineer will be responsible for developing and optimizing RTL-to-GDSII physical designs using industry-standard EDA tools, ensuring compliance with CMOS digital design principles and standard cell libraries. Day-to-day tasks include implementing DFT/Scan/LBIST techniques and collaborating on physical design flows to enhance chip performance and reliability. Candidates should have 3+ years of professional experience in physical design or related fields, proficiency in EDA toolsets, and a solid understanding of CMOS digital design principles. The role requires expertise in scripting languages like Perl or Python for automation and script development within the context of large-scale semiconductor projects.

Skills

EDA tools CMOS digital design principles standard cells DFT Scan MBIST LBIST RTL2GDSII physical design flow development

What you'll do

Develop and optimize physical design flows for RTL2GDSII processes.
Utilize industry-standard EDA tools for efficient chip design.
Apply CMOS digital design principles in creating standard cells.
Implement DFT/Scan/LBIST techniques to enhance testability.
Collaborate on the development of advanced physical design methodologies.

What we're looking for

3+ years of professional experience in RTL2GDSII physical design or flow development
Proficiency with industry-standard EDA tools and understanding of their capabilities and algorithms
Knowledge of CMOS digital design principles, standard cells, and libraries
Basic knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows
ITAR compliance for U.S. Department of State requirements

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