RTL Design Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $125,000–$145,000 / yr
Posted: today

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $184k

This role $135k

$113k most similar roles pay here $233k

This role pays less than 87% of similar roles. Most pay $153,100–$215,125 — the shaded band above. At the midpoint, this role pays about $135k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · RTL Design Engineer (Silicon Engineering)

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Join the Starlink team as an ASIC Design Engineer, contributing to the development of advanced integrated circuits and FPGAs for satellite communication systems. You will design complex SoCs using Verilog/SystemVerilog, engage in high-level architectural discussions, and collaborate with backend teams throughout the entire lifecycle of FPGA and ASIC projects. Your daily tasks include scripting with Python, working on DSP or digital communication system datapath blocks, and understanding AXI/AHB/APB protocols while utilizing EDA tools for simulation and verification. This role requires a strong background in electrical engineering and experience in RTL design, making it ideal for those passionate about cutting-edge technology in the aerospace and satellite communications domain.

Skills

SystemVerilog Verilog Python DSP AXI AHB APB EDA tools HDL simulators

What you'll do

Design ASICs and/or FPGAs for Starlink projects using Verilog/SystemVerilog.
Participate in the full lifecycle of FPGA/ASIC design, from conceptual to validation phases.
Engage in high-level architectural design for complex SoCs within the Starlink program.
Collaborate on developing new technologies impacting User terminals and Satellites.
Assist in lab bring-up and validation tasks during integration stages.

What we're looking for

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
1+ years of experience in RTL Design using SystemVerilog, Verilog, or VHDL
Master’s in Electrical/Computer Engineering or related field
Experience with EDA tools and AXI/AHB/APB protocols
Proficiency in Python for scripting and strong foundation in electrical engineering fundamentals

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