RTL Design Engineer, Silicon Engineering

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$125,000–$145,000 / yr
Posted
178 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k
This role $135k
$112k most similar roles pay here $243k

This role pays less than 92% of similar roles. Most pay $167,100–$217,500 — the shaded band above. At the midpoint, this role pays about $135k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · RTL Design Engineer, Silicon Engineering

Role Posting Log in to save

The RTL Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation FPGAs and ASICs for deployment in space and ground infrastructures. This role involves the full ASIC and FPGA design lifecycle, including high-level conceptual architectural discussions, microarchitecture, design partitioning, and collaboration with backend teams. The engineer will implement IP for complex SoCs and assist in lab bring-up and validation to enhance the performance of the Starlink network. Key technical requirements include proficiency in Verilog, SystemVerilog, or VHDL, along with experience in Python scripting and EDA tools like HDL simulators. Candidates should possess a strong foundation in electrical engineering fundamentals and knowledge of AXI, AHB, and APB protocols. The role specifically addresses the challenge of providing reliable connectivity through advanced hardware for satellite systems and user terminals.

Skills

RTL Design SystemVerilog Verilog VHDL ASIC FPGA Python DSP AXI AHB APB EDA Tools HDL Simulators

What you'll do

  • Design ASICs and FPGAs for Starlink projects using Verilog and SystemVerilog.
  • Implement IP for complex Systems on a Chip (SoCs).
  • Participate in the full ASIC/FPGA design lifecycle from conceptual architecture to microarchitecture.
  • Perform design partitioning and collaborate with backend implementation teams.
  • Assist in lab bring-up and validation of hardware components.
  • Engage in high-level architectural design for space and ground infrastructure electronics.
  • Develop new technologies for Starlink user terminals and satellites.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog, or VHDL.
  • Master’s degree in Electrical/Computer Engineering or a related field is preferred.
  • Experience with ASIC/FPGA system integration and designing DSP or digital communication system datapath blocks.
  • Proficiency in Python for scripting and experience with EDA tools such as HDL simulators.
  • Understanding of AXI, AHB, and APB protocols.
  • Strong foundation in electrical engineering fundamentals.
  • Must be a U.S. citizen, permanent resident, refugee, or asylee to meet ITAR requirements.

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