New Graduate Engineer, Silicon Engineering

SpaceX

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Palo Alto, CAIrvine, CARedmond, WA
Salary
$125,000–$160,000 / yr
Posted
28 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $195k
This role $142k
$112k most similar roles pay here $248k

This role pays less than 90% of similar roles. Most pay $162,000–$227,350 — the shaded band above. At the midpoint, this role pays about $142k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · New Graduate Engineer, Silicon Engineering

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New Graduate Engineer, Silicon Engineering will join the team to develop next-generation silicon for the Starlink program. This role involves participating in all phases of ASIC and FPGA design and verification flows, including architecture, RTL implementation, and emulation. Candidates will perform lab bring-up and validation using C/C++ or Python, while others may focus on RF/Analog IC design, modeling systems at a high level, and developing circuits in SiGe or CMOS processes. The position also involves digital signal processing using SystemVerilog to develop blocks for communication systems, as well as physical design tasks like synthesis, floor planning, and timing analysis. Required skills include experience with ASIC, SOC, FPGA, RFIC, or MMIC technologies, along with proficiency in tools such as ADS, Spectre, HFSS, or Momentum to solve complex hardware and software integration challenges.

What does a Engineer earn in California?

Median $208000 from 94 postings across 22 companies.

See salary data

Skills

ASIC FPGA RTL Design SystemVerilog Verilog VHDL C++ Python RFIC MMIC DSP MATLAB ADS Spectre HFSS Momentum CMOS Physical Design Synthesis tapeout

What you'll do

  • Participate in all phases of ASIC and FPGA design and verification flows.
  • Develop RTL designs using SystemVerilog for DSP and digital communication system blocks.
  • Bring up and validate ASICs and FPGAs in the lab using C/C++ or Python.
  • Simulate and model RFIC systems to partition functions between hardware and software domains.
  • Develop RF and microwave circuits using state-of-the-art SiGe or CMOS processes.
  • Perform physical design steps including synthesis, floor planning, place and route, and timing analysis.
  • Create automation scripts to improve physical design methodologies and implementation steps.
  • Execute the full verification of complex digital designs for Starlink SOCs.

What we're looking for

  • Must be graduating with a bachelor's, master's, or PhD in 2026 or 2027.
  • Degree must be in an engineering discipline, mathematics, or physics.
  • Experience working with ASIC, SOC, FPGA, RFIC, or MMIC.
  • Ability to work extended hours and weekends as necessary to meet critical project milestones.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee (or eligible for such status) per ITAR regulations.
  • Understanding of computer architecture (preferred).
  • Experience in analog/digital CMOS IC design, physical design, SystemVerilog, Verilog, VHDL, C/C++, or Python (preferred).
  • Bachelor’s degree in an engineering discipline, mathematics or physics.

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