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Active Keyword: Design Verification Engineer Remove filter Location: Irvine Remove filter Clear all

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Design Verification Engineer

Broadcom

Broomfield, CO +4 38 days ago $143,800–$230,000
Actively hiring Confirmed live 2 days ago High trust Competitive pay
SystemVerilog UVM SVA RTL Gate-level Netlists Python Perl Tcl Git FPGA Emulation Synopsys Cadence Mentor Co-simulation iJTAG Tessent DesignSync
10+ yrs exp
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Design Verification Engineer, Silicon Engineering

SpaceX

Irvine, CA 59 days ago $125,000–$145,000
Actively hiring Confirmed live 2 days ago Low trust Below market
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 59 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage
5+ yrs exp
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Principal Design Verification Engineer

SpaceX

Irvine, CA 113 days ago $210,000–$335,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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