Wireless Radio Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $175,000–$308,500 / yr
Posted: 15 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $242k

$131k most similar roles pay here $327k

This role pays more than 82% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $242k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · Wireless Radio Verification Engineer

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As a Wireless Radio Verification Engineer, you will join the Wireless Connectivity team to ensure first-time-right silicon success for WiFi SoCs. You will lead the verification of radio digital controllers and Digital+RF subsystems, focusing on complex transceiver paths including PLLs, DAC/ADC data paths, power management, and co-existence mechanisms. Your daily work involves architecting UVM testbench environments, developing constrained random scenarios for complex protocols, and leading digital and mixed-signal co-simulation efforts using SystemVerilog behavioral models and DMS. You will collaborate across design, RF, PHY, and systems teams to resolve issues at the intersection of digital design and RF/mixed-signal-modeled systems. Required skills include expertise in SystemVerilog, UVM, functional coverage, assertion-based verification, and Python for automation. The role addresses technical challenges in multi-gigabit wireless technology across diverse scenarios and environmental conditions.

Skills

SystemVerilog UVM ASIC Verification Mixed-Signal Co-simulation Python Functional Coverage Assertion-Based Verification PLL DAC ADC Digital Design Verification Planning Scripting

What you'll do

Lead subsystem-level verification of radio digital controllers and data paths from planning through feature closure.
Architect sophisticated UVM testbench environments for radio control systems, PLL controllers, and data path subsystems.
Develop constrained random scenarios for complex radio protocols and multi-domain interactions.
Lead digital and mixed-signal co-simulation efforts using SystemVerilog behavioral models and DMS.
Define verification requirements and debug complex issues across digital and RF/analog domains.
Establish best practices and mentor team members on radio verification methodologies.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
Demonstrated expertise verifying complex digital ASICs with a track record of successful silicon tapeouts.
Deep knowledge of ASIC verification flows using SystemVerilog and UVM, including testbench architecture and coverage-driven methodologies.
Experience developing verification environments from scratch and bringing up complex designs in simulation.
Experience with constrained random testing, functional coverage, and assertion-based verification.
Experience verifying radio digital controllers, DSPs, PLL control systems, or wireless transceiver subsystems (preferred).
Exposure to RF/analog system designs such as LNAs, Mixers, PLLs, amplifiers, LDOs, DAC/ADCs (preferred).
Experience with digital and mixed-signal co-simulation using SystemVerilog behavioral models or real-number modeling (preferred).

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