Design Verification Engineer

Amazon Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TXIrvine, CASan Diego, CA
Salary: $153,600–$215,000 / yr
Posted: 33 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $178k

This role $184k

$135k most similar roles pay here $224k

This role pays more than 66% of similar roles. Most pay $160,000–$196,887 — the shaded band above. At the midpoint, this role pays about $184k versus about $178k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 535 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 533 roles with salary data.

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View all roles at Amazon Inc

At a glance

TL;DR · Design Verification Engineer

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Design Verification Engineer, Amazon Leo will join the sub-team responsible for defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and gateways. The role involves building state-of-the-art verification environments for IP, subsystems, and SOCs to test devices against reference models. Daily responsibilities include developing detailed test plans, writing tests, running regressions, collecting coverage matrices, and debugging system-level communication scenarios in both pre-silicon and post-silicon environments. The candidate will also develop highly automated environments to triage regression fails. Key technical requirements include experience with UVM, C, SystemC, DPI-C, and scripting. Preferred skills include Matlab, formal verification techniques, modem design verification, and utilizing AI/LLM tools for test generation and debug. This role addresses the challenge of creating groundbreaking wireless solutions using latest CMOS technologies for satellite communication systems.

What does a Design Verification Engineer earn?

Median $195800 from 64 postings across 10 companies.

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Skills

UVM SystemC DPI-C C Matlab Formal Verification pre silicon post silicon SOC CMOS LLM AI Scripting Digital Verification Modem Design

What you'll do

Implement state-of-the-art verification environments for IP, subsystems, and SOCs to test devices against reference models.
Develop detailed test plans and write tests to execute regressions and collect coverage matrices.
Debug system-level communication scenarios in both pre-silicon and post-silicon environments.
Participate in system-level verification using test benches constructed with UVM, SystemC, and DPI-C.
Build highly automated environments to triage regression failures and report issues to stakeholders.
Integrate and verify modem designs, high-speed interfaces, and DSP solutions in latest CMOS technologies.

What we're looking for

Bachelor's degree in Electrical Engineering or a related field.
2+ years of experience with UVM, C, SystemC, and scripting.
5+ years of experience in verification (preferably in communication systems).
Must be a U.S. citizen, national, permanent resident, or granted asylum/refugee status for export control compliance.
Master's or Ph.D. degree in Electrical or Communications Engineering (preferred).
7+ years in digital verification, preferably in communication systems (preferred).
Proficiency in leveraging AI/LLM tools to accelerate verification workflows (preferred).
Experience with Matlab, modem design, formal verification, or SystemC/Matlab model integration (preferred).