SOC Design Verification Engineer

Apple Inc

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $175,000–$308,500 / yr
Posted: 11 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k

This role $242k

$131k $327k

below market most similar roles pay here above market

This role pays more than 85% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $242k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SOC Design Verification Engineer

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The SOC Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification at the block, subsystem, and top-level SOC levels. You will own a verification scope from test planning through coverage closure and signoff, building reusable testbenches and verification environments using metric-driven methodologies. Key responsibilities include writing directed and constrained-random tests, debugging failures, and verifying low-power design intent using UPF. You will work on components like the Power Management Unit, CPU subsystem, DMA, PCIe, and bus fabric. Required skills include SystemVerilog, Verilog, and UVM, with experience in digital logic design and SOC architecture. You will also verify WiFi and Bluetooth traffic flows and explore AI-assisted verification techniques to improve productivity within the wireless chip design domain.

Skills

SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA ASIC SOC PCIe AXI AHB WiFi Bluetooth AI/ML

What you'll do

Develop reusable block, IP, and subsystem-level UVM testbenches for SOC integration.
Create directed and constrained-random tests to drive coverage closure and verification signoff.
Debug hardware failures and corner cases while managing the bug tracking process.
Verify low-power design intent using UPF within assigned blocks and subsystems.
Verify end-to-end WiFi and Bluetooth traffic flows from subsystem to top-level SOC integration.
Build and improve automated regression flows and contribute to verification methodology.
Explore and apply AI-assisted verification techniques for test generation and debugging.
Support post-silicon bring-up activities as needed.

What we're looking for

BS degree and a minimum of 10 years of relevant industry experience.
Hands-on experience across the verification cycle including test planning, testbench implementation, test creation, debug, and coverage closure.
Strong SystemVerilog and Verilog skills with solid working knowledge of UVM.
Solid problem-solving and debugging skills with constrained-random verification.
Understanding of digital logic design, SOC architecture, and microarchitecture.
Experience taking at least one ASIC/SOC from concept through tape-out (preferred).
Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment (preferred).
Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols (preferred).

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