Senior Design Verification Engineer

Amazon Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Irvine, CASan Diego, CASunnyvale, CAAustin, TX
Salary: $185,200–$250,000 / yr
Posted: 33 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $183k

This role $218k

$137k most similar roles pay here $262k

This role pays more than 90% of similar roles. Most pay $169,050–$197,750 — the shaded band above. At the midpoint, this role pays about $218k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 535 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 533 roles with salary data.

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View all roles at Amazon Inc

At a glance

TL;DR · Senior Design Verification Engineer

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Sr. Design Verification Engineer, Amazon Leo joins the sub-team responsible for defining and implementing digital chip SOCs for communication via Low Earth Orbit satellites and gateways. This role involves building state-of-the-art verification environments for IP, subsystems, and SOCs to facilitate testing against reference models. The engineer will develop detailed test plans, write tests, run regressions, collect coverage matrices, and build highly automated environments to triage regression fails. Key responsibilities include debugging system-level communication scenarios in both pre-silicon and post-silicon environments. To succeed, the candidate must possess expertise in UVM, C, SystemC, DPI-C, and scripting. Preferred skills include Matlab, formal verification techniques, and leveraging AI/LLM tools to accelerate workflows. The role focuses on solving complex communication problems by developing modems, high-speed interfaces, embedded processors, and DSP solutions using the latest CMOS generation technologies.

What does a Design Verification Engineer earn?

Median $195800 from 64 postings across 10 companies.

See salary data

Skills

UVM SystemC DPI-C C Matlab Formal Verification Scripting pre silicon post silicon AI/LLM Tools Modem Design CMOS

What you'll do

Implement state-of-the-art verification environments for IP, subsystems, and SOCs to test designs against reference models.
Develop detailed test plans and write tests to verify system functionality.
Execute regression tests and collect coverage matrices to report progress to program stakeholders.
Debug system-level communication scenarios in both pre-silicon and post-silicon environments.
Build and utilize test benches using UVM, SystemC, and DPI-C for system-level verification.
Develop highly automated environments to triage regression failures and report issues to stakeholders.

What we're looking for

Must be a U.S. citizen, national, permanent resident, or granted asylum/refugee status for export control compliance.
Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering.
3+ years of experience with UVM, C, SystemC, and scripting.
7+ years of experience in verification (preferably in communication systems).
Master's or Ph.D. degree in Electrical or Communications Engineering (preferred).
10+ years in digital verification, preferably in communication systems (preferred).
Proficiency in AI/LLM tools for verification workflows, Matlab, and formal verification techniques (preferred).
Experience with modem design, SystemC/Matlab model development, and strong communication skills (preferred).