Wireless Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $175,000–$308,500 / yr
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $242k

$131k $327k

below market most similar roles pay here above market

This role pays more than 82% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $242k versus about $205k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3595 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2772 roles with salary data.

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At a glance

TL;DR · Wireless Design Verification Engineer

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The Wireless Design Verification Engineer joins the Wireless Connectivity team to ensure first-time-right silicon success for WiFi SoCs. This role involves leading subsystem-level verification of Radio digital controllers and Digital+RF subsystems, specifically focusing on PLLs, DAC/ADC data paths, power management, and co-existence mechanisms. You will architect sophisticated UVM testbench environments, develop constrained random scenarios for complex radio protocols, and lead digital and mixed-signal co-simulation efforts. The position requires deep expertise in SystemVerilog, UVM, and coverage-driven methodologies to verify complex digital ASICs. You will work at the intersection of digital design and RF/mixed-signal-modeled systems, solving problems related to robust wireless operation across diverse scenarios. Key skills include experience with behavioral models, real-number-modeling, and Python scripting for automation and analysis.

Skills

SystemVerilog UVM ASIC Verification Mixed-Signal Co-simulation Functional Coverage Assertion-Based Verification Python PLL DAC ADC RF Digital Design Verification Planning DMS Models

What you'll do

Lead subsystem-level verification of Radio digital controllers and data paths from planning through closure.
Architect UVM testbench environments and infrastructure for radio control systems and PLL controllers.
Develop constrained random scenarios for complex radio protocols and multi-domain interactions.
Lead digital and mixed-signal co-simulation efforts using SystemVerilog behavioral and DMS models.
Define verification requirements and debug complex issues spanning digital and RF/analog domains.
Establish verification strategies and best practices for radio-modeled subsystems.
Mentor team members on radio verification approaches and technical best practices.

What we're looking for

BS degree and a minimum of 10 years of relevant industry experience.
Demonstrated expertise verifying complex digital ASICs with a track record of successful silicon tapeouts.
Deep knowledge of ASIC verification flows with SystemVerilog and UVM, including testbench architecture and coverage-driven methodologies.
Experience developing verification environments from scratch and bringing up complex designs in simulation.
Experience with constrained random testing, functional coverage, and assertion-based verification.
Experience verifying Radio digital controllers, DSPs, PLL control systems, or wireless transceiver subsystems (preferred).
Exposure to RF/analog system designs such as LNAs, Mixers, PLLs, amplifiers, LDOs, DAC/ADCs (preferred).
Experience with digital + mixed-signal co-simulation using SystemVerilog analog behavioral models or real-number-modeling (preferred).