Browse tech roles

UVM SystemVerilog Python C++ Java SoC Digital Design Computer Architecture Low Power Architecture Multi-chip SoC Debug High Speed Protocols +6 more Show less

UVM RTL Verification UPF PCIe AXI AHB NoC SPI I2C UART DMA Formal Verification Low Power Design SoC Architecture Coverage Driven Verification +10 more Show less

System Verilog UVM C Python SVA RTL Assertion-Based Verification Coverage-Driven Verification Portable Stimulus Formal Verification Emulation LLM RAG PCIe Ethernet CXL HBM DDR Cache Coherency +14 more Show less

System Verilog UVM C SVA Python Coverage-Driven Verification Formal Verification Portable Stimulus (PSS) RTL PCIe CXL DDR HBM Ethernet Veloce Palladium ZeBu Emulation ASIC Design +14 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC IC Packages +6 more Show less

System Verilog UVM C SVA Python Coverage-Driven Verification Formal Verification Portable Stimulus (PSS) Emulation Veloce Palladium ZeBu PCIe CXL Ethernet DDR HBM RTL ASIC Design +14 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

ASIC RTL GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting SoC +5 more Show less

System Verilog UVM C SVA Python Coverage-Driven Verification Formal Verification Portable Stimulus (PSS) Emulation Veloce Palladium ZeBu PCIe CXL Ethernet DDR HBM RTL ASIC Design +14 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC +5 more Show less

LVS DRC ANT HVDRC Mentor Calibre Synopsys ICV Python Perl Tcl ASIC Layout Design Tapeout RDL Padring Bump Mixed Signal Physical Verification +12 more Show less

LVS DRC ANT HVDRC Mentor Calibre Synopsys ICV Python Perl Tcl ASIC Physical Design Tapeout Layout Design RDL Design-for-Manufacturing Design-for-Yield Lithography +11 more Show less

LVS DRC ANT HVDRC Mentor Calibre Synopsys ICV Python Perl Tcl ASIC Tapeout Layout Design RDL Padring Bump Mixed Signal Signoff Flow +12 more Show less

System Verilog UVM Verilog C++ C Python Perl SOC Architecture Computer Architecture AXI AHB PCIe DDR Functional Verification Performance Verification Code Coverage Functional Coverage +12 more Show less

LVS DRC ANT HVDRC Mentor Calibre Synopsys ICV Python Perl Tcl ASIC Tapeout Layout Design RDL Padring Bump Mixed Signal Lithography +12 more Show less

LVS DRC ANT HVDRC Mentor Calibre Synopsys ICV Python Perl Tcl ASIC Tapeout Layout Design RDL Padring Bump Design-for-Manufacturing Design-for-Yield +12 more Show less