SoC Physical Design Verification Engineer

As a SoC Physical Design Verification Engineer within the Silicon Technologies group, you will perform critical physical verification checks at both the chip and block levels to ensure successful tapeout. Your daily responsibilities include executing LVS, DRC, design-for-manufacturing, and lithography checks while collaborating with CAD and Technology teams for flow bring up and validation. You will work closely with implementation teams throughout the design cycle to drive signoff closure and manage schedules for cross-functional engineering efforts. The role involves specific work on padring, bump, RDL design, and coordination with package and floorplan teams. Required skills include proficiency in Mentor Calibre or Synopsys ICV tools, experience with ESD and macro placement guidelines, and scripting capabilities in Perl, Python, or Tcl to automate checks and debug flow issues for high-performance, power-efficient system-on-chip designs.