SOC Design Verification Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
15 days ago
Freshness
Confirmed live 2 days ago
Closes
Feb 23, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k
This role $144k
$102k most similar roles pay here $238k

This role pays less than 85% of similar roles. Most pay $162,000–$216,250 — the shaded band above. At the midpoint, this role pays about $144k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · SOC Design Verification Engineer

The SOC Design Verification Engineer joins the Data Center SoC Verification team to verify next-generation SoCs powering AI, high-performance computing, and cloud infrastructure. The role involves developing and executing comprehensive verification plans for SoC, subsystem, and IP-level features while building scalable System Verilog/UVM-based and Processor-based environments. Key responsibilities include creating directed and constrained-random test scenarios, developing assertions and functional coverage models, and debugging RTL and testbench issues to ensure first-silicon success. The candidate will work with multi-core CPUs, cache coherency systems, memory subsystems, AI/ML accelerators, and high-speed interconnects like PCIe, CXL, and Ethernet. Required skills include System Verilog, UVM, C, Assertion-Based Verification, and Python for automation. The role addresses complex technical challenges in SoC architecture, including security, RAS features, and power management within the semiconductor industry.

What you'll do

  • Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
  • Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
  • Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
  • Develop assertions, functional coverage models, and checkers to ensure design integrity.
  • Debug RTL, testbench, and integration issues while working with design teams to resolve defects.
  • Drive coverage closure using both functional and code coverage metrics.
  • Verify complex Data Center features including multi-core CPUs, memory subsystems, and high-speed interconnects.
  • Contribute to methodology improvements, automation, and AI-assisted verification flows.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Master's degree in Science, Engineering, or a related field.
  • PhD in Science, Engineering, or a related field.
  • Minimum 2+ years of ASIC design, verification, validation, integration, or related work experience for Bachelor's holders.
  • Minimum 1+ year of ASIC design, verification, validation, integration, or related work experience for Master's holders.
  • Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), and Coverage-Driven Verification.
  • Experience developing verification environments from architecture/specification through signoff.
  • Proficiency in Python or other scripting languages for automation and AI-assisted verification workflows.

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