SOC Design Verification Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$121,800–$182,600 / yr
Posted
50 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $152k
$109k $240k
below market most similar roles pay here above market

This role pays less than 88% of similar roles. Most pay $168,500–$217,700 — the blue band above. At the midpoint, this role pays about $152k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$218,400 across 551 roles with salary data.

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At a glance

TL;DR · SOC Design Verification Engineer

The SOC Design Verification Engineer – Data Center Solutions joins the Data Center SoC Verification team to verify next-generation SoCs for AI, high-performance computing, and cloud infrastructure. The engineer develops comprehensive verification plans, designs scalable System Verilog and UVM-based environments, and creates directed and constrained-random test scenarios. Key responsibilities include developing assertions, functional coverage models, and checkers while debugging RTL and testbench issues to ensure first-silicon success. The role requires proficiency in System Verilog, UVM, C, Assertion-Based Verification, and Coverage-Driven Verification. Candidates will work on complex features including multi-core CPUs, cache coherency, DDR/HBM memory subsystems, PCIe, CXL, and Ethernet. The work involves solving technical challenges in SoC architecture, security, RAS, and power-management features using tools like Portable Stimulus and emulation platforms.

What you'll do

  • Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
  • Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
  • Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
  • Develop assertions, functional coverage models, and checkers to ensure design integrity.
  • Debug RTL, testbench, and integration issues to resolve defects in collaboration with design teams.
  • Drive coverage closure using functional and code coverage metrics.
  • Verify complex features including multi-core CPUs, cache coherency, memory subsystems, and high-speed interfaces.
  • Contribute to methodology improvements, automation, and AI-assisted verification flows.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field.
  • Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), Coverage-Driven Verification, and System level Use case verification.
  • Experience developing verification environments from architecture/specification through signoff.
  • Strong understanding of computer architecture and digital design fundamentals.
  • Experience debugging complex SoC-level issues.
  • Experience with CPU, cache coherency, memory systems, networking protocols, or AI/ML accelerator verification (preferred).

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