SOC Design Verification Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$121,800–$182,600 / yr
Posted
4 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k
This role $152k
$109k most similar roles pay here $238k

This role pays less than 83% of similar roles. Most pay $164,437–$218,375 — the shaded band above. At the midpoint, this role pays about $152k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 615 open roles on FindRole.

Listed pay typically runs $155,400–$232,600 across 593 roles with salary data.

Most-posted roles

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At a glance

TL;DR · SOC Design Verification Engineer

Role Posting Log in to save

The SOC Design Verification Engineer – Data Center Solutions joins the Data Center SoC Verification team to verify next-generation SoCs powering AI, high-performance computing, and cloud infrastructure. You will develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features while building scalable System Verilog/UVM-based and Processor-based environments. Daily responsibilities include creating directed and constrained-random test scenarios, developing assertions and functional coverage models, and debugging RTL and testbench issues to ensure first-silicon success. You will work with multi-core CPUs, cache coherency systems, memory subsystems like DDR/HBM, and high-speed interfaces including PCIe, CXL, and Ethernet. Required skills include System Verilog, UVM, C, Assertion-Based Verification, and Python for automation. The role addresses complex technical challenges in advanced SoC architecture, including security, RAS features, and AI/ML accelerator verification within the data center domain.

Skills

System Verilog UVM C SVA Python Coverage-Driven Verification Formal Verification Portable Stimulus (PSS) Emulation Veloce Palladium ZeBu PCIe CXL Ethernet DDR HBM RTL ASIC Design

What you'll do

  • Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
  • Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
  • Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
  • Develop assertions, functional coverage models, and checkers to ensure design integrity.
  • Debug RTL, testbench, and integration issues while working with design teams to resolve defects.
  • Drive coverage closure using both functional and code coverage metrics.
  • Verify complex Data Center SoC features including multi-core CPUs, memory subsystems, and high-speed interconnects.
  • Contribute to methodology improvements, automation, and AI-assisted verification flows.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field (Master's or PhD also acceptable).
  • Minimum 2+ years of ASIC design, verification, validation, or integration experience for Bachelor's holders; 1+ year for Master's holders.
  • Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), and Coverage-Driven Verification.
  • Experience developing verification environments from architecture/specification through signoff.
  • Strong understanding of computer architecture and digital design fundamentals.
  • Experience debugging complex SoC-level issues.
  • Proficiency in Python or scripting languages for automation (preferred).
  • Experience with specific protocols, hardware platforms, or advanced verification methodologies like PSS, Formal, or Emulation (preferred).

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