SoC Physical Design Verification Engineer

What you'll do

• Perform physical verification checks including LVS, DRC, DFM, and lithography at the chip and block levels.
• Drive signoff closure for tapeout in coordination with the implementation team throughout the design cycle.
• Collaborate with CAD and Technology teams to perform flow bring-up and validation.
• Manage project schedules and support cross-functional engineering efforts.
• Design padring, bump, and RDL components while coordinating with package and floorplan teams.
• Execute mixed-signal back-end verification checks including ESD and macro placement guidelines.
• Develop scripts in Perl, Python, or Tcl to debug flow issues and automate verification checks.

What we're looking for

• Bachelor of Science degree and 3+ years of relevant industry experience.
• Experience with physical verification flows such as DRC, LVS, ANT, and HVDRC signoff (preferred).
• Experience with ESD, macro placement design guidelines, and mixed-signal back-end verification (preferred).
• Knowledge of all aspects of ASIC physical design and physical verification checks (preferred).
• Scripting skills in Perl, Python, or Tcl to debug flows and automate checks (preferred).
• Experience with industry standard tools like Mentor Calibre or Synopsys ICV (preferred).
• Tapeout experience with a track record of successful signoff (preferred).
• Layout design experience (preferred).