SoC Physical Design Verification Engineer

As a SoC Physical Design Verification Engineer within the Silicon Technologies group, you will join a critical team responsible for the physical verification of high-performance, power-efficient system-on-chip designs. Your daily responsibilities include performing various physical verification checks such as LVS, DRC, design-for-manufacturing, and lithography at both the chip and block levels. You will collaborate with CAD and Technology teams for flow bring up while working with implementation teams to drive signoff closure for tapeout. Additionally, you will manage schedules, support cross-functional engineering efforts, and work on padring, bump, and RDL design. Required skills include experience with DRC/LVS/ANT/HVDRC flows, ESD guidelines, and mixed signal back-end verification. You should be proficient in industry standard tools like Mentor Calibre or Synopsys ICV, along with scripting in Perl, Python, or Tcl to automate checks.