GSoC Design Verification Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $101,400–$152,200 / yr
Posted: 34 days ago
Freshness: Confirmed live today
Closes: Mar 22, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k

This role $127k

$86k $246k

below market most similar roles pay here above market

This role pays less than 98% of similar roles. Most pay $168,500–$230,087 — the blue band above. At the midpoint, this role pays about $127k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · GSoC Design Verification Engineer

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The GSoC Design Verification Engineer joins the GSoC HW team within the Global SoC organization to verify next-generation Data Center SoCs. This role involves ensuring the quality and functionality of complex designs including multi-core CPUs, cache coherency systems, memory subsystems, and AI/ML accelerators. You will develop and execute comprehensive verification plans, implement scalable System Verilog/UVM-based and Processor-based environments, and create constrained-random test scenarios. Key responsibilities include debugging RTL issues, driving coverage closure, and building AI-powered intelligent agents using modern LLM frameworks and RAG pipelines to automate engineering tasks like regression management and test planning. Required skills include System Verilog, UVM, C, Assertion-Based Verification, and Python. You will solve technical challenges in high-performance computing, mobile, and cloud infrastructure products.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

System Verilog UVM C Assertion-Based Verification (SVA) Python Coverage-Driven Verification RTL Formal Verification Portable Stimulus (PSS) LLM RAG PCIe Ethernet DDR HBM Veloce Palladium ZeBu Cache Coherency ACE CHI CXL

What you'll do

Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
Develop assertions, functional coverage models, and checkers to ensure design quality.
Debug RTL, testbench, and integration issues to resolve defects in complex SoC designs.
Drive coverage closure using functional and code coverage metrics.
Build AI-powered intelligent agents and workflows using modern LLM frameworks to automate engineering tasks.
Develop Retrieval Augmented Generation (RAG) pipelines for system documentation and engineering knowledge.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field.
Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), Coverage-Driven Verification, and system-level use case verification.
Experience developing verification environments from architecture and specification through signoff.
Strong understanding of computer architecture and digital design fundamentals.
Experience debugging complex SoC-level issues.
Proficiency in Python or scripting languages for automation.
Experience with AI-assisted verification of workflows and test generation.
Experience in full-chip or subsystem verification environments (preferred).

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