This role pays less than
92%
of similar roles. Most pay
$159,937–$216,250
— the shaded band above.
At the midpoint, this role pays about
$123k
versus about
$188k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
The GSoC Design Verification Engineer joins the GSoC HW team to verify next-generation Data Center SoCs powering AI, high-performance computing, and cloud infrastructure. This role involves developing scalable System Verilog and UVM-based verification environments, creating test plans, and executing tests to ensure functionality for complex SoC designs including multi-core CPUs, memory subsystems, and AI/ML accelerators. The engineer will also build AI-powered intelligent agents using modern LLM frameworks and RAG pipelines to automate tasks like regression management and debug automation. Key technical requirements include proficiency in System Verilog, UVM, C, SVA, Python, and coverage-driven verification. Candidates must possess a strong understanding of computer architecture and digital design fundamentals while navigating complex domains such as cache coherency protocols, high-speed interconnects, and security features to ensure first-silicon success for advanced hardware products.
Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
Develop assertions, functional coverage models, and checkers to drive coverage closure.
Debug RTL, testbench, and integration issues while collaborating with design teams to resolve defects.
Support emulation and acceleration-based verification for complex Data Center SoC features.
Build AI-powered intelligent agents using LLM frameworks to automate engineering tasks like regression management and debug automation.
Develop RAG pipelines and integrate AI systems with engineering tools, databases, and knowledge repositories.
What we're looking for
Bachelor's or master's degree in electrical engineering, computer engineering, computer science, or a related field.
Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), and Coverage-Driven Verification.
Experience developing verification environments from architecture/specification through signoff.
Strong understanding of computer architecture and digital design fundamentals.
Experience debugging complex SoC-level issues.
Proficiency in Python or other scripting languages for automation.
Experience with AI-assisted verification of workflows and test generation.
Experience with CPU, memory systems, networking protocols, or AI/ML accelerator verification (preferred); knowledge of LLMs and Generative AI (preferred).
System Verilog
UVM
SystemC
Verilog
C++
Formal Verification
ASIC Design
RTL
Linux
Windows
OOP
Simulation
Functional Coverage
Digital Design
Computer Architecture