Design Verification Engineer, Cellular SoC

Apple Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $129,300–$194,700 / yr
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k

This role $162k

$117k most similar roles pay here $244k

This role pays less than 80% of similar roles. Most pay $168,500–$231,737 — the shaded band above. At the midpoint, this role pays about $162k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer, Cellular SoC

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As a Design Verification Engineer - Cellular SoC, you will join the silicon design group responsible for crafting and productizing innovative Cellular SoCs. You will be at the center of the verification effort, where you will integrate multiple sophisticated IP level DV environments and craft highly reusable UVM based test benches. Your daily work involves implementing coverage driven and advised test suites while deploying new tools and methodologies to ensure chips are right-first-time. The role requires proficiency in SystemVerilog, Python, C++, or Java. You will navigate complex technical domains including high speed protocols, low power architecture, cellular protocols, and firmware-hardware interactions. By collaborating with various product development groups, you will solve problems related to multi-chip SoC debug architectures and the integration of hardware elements into a single, coordinated design for wireless systems.

What does a Design Verification Engineer earn in California?

Median $191200 from 59 postings across 7 companies.

See salary data

Skills

UVM SystemVerilog Python C++ Java SoC Digital Design Computer Architecture Low Power Architecture Multi-chip SoC Debug High Speed Protocols

What you'll do

Integrate multiple sophisticated IP level verification environments into the SoC design.
Create highly reusable UVM based test benches for cellular systems.
Implement coverage-driven and advised test suites to ensure chip quality.
Deploy new tools and methodologies to achieve right-first-time silicon delivery.
Verify high-speed protocols and low-power architectures within the cellular SoC.
Debug complex multi-chip SoC architectures and firmware-hardware interactions.
Perform verification on accelerated platforms to validate system performance.

What we're looking for

A Bachelor of Science degree is required.
Programming experience in SystemVerilog, Python, C++, or Java is required.
A Master's degree in Electrical Engineering or Computer Science is preferred.
Coursework in Digital Design, Computer Architecture, Object Oriented Programming, and Networking Protocol is preferred.
Excellent communication and problem-solving skills are required.

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