Design Verification Engineer
Apple Inc
Quick summary
Market check
How this pay compares to similar roles
This role pays less than 89% of similar roles. Most pay $168,500–$227,350 — the shaded band above. At the midpoint, this role pays about $152k versus about $198k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 568 open roles on FindRole.
Listed pay typically runs $150,615–$222,050 across 554 roles with salary data.
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At a glance
The SOC Design Verification Engineer joins the Data Center SoC Verification team to verify next-generation SoCs powering AI, high-performance computing, and cloud infrastructure. You will develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features while building scalable System Verilog/UVM-based and Processor-based verification environments. Daily responsibilities include creating directed and constrained-random test scenarios, developing assertions and functional coverage models, and debugging RTL and testbench issues to ensure first-silicon success. You will work with complex components including multi-core CPUs, cache coherency systems, memory subsystems like DDR/HBM, and high-speed interfaces such as PCIe and Ethernet. Required skills include System Verilog, UVM, C, Assertion-Based Verification, and Python for automation. The role addresses technical challenges in advanced SoC architecture, including security, power management, and AI/ML accelerator verification within a complex data center environment.
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