SoC Physical Design Verification Engineer

As a SoC Physical Design Verification Engineer within the Silicon Technologies group, you will join a critical team responsible for the physical verification of high-performance, power-efficient system-on-chip designs. Your daily responsibilities involve performing essential physical verification checks including LVS, DRC, design-for-manufacturing, design-for-yield, and lithography at both the chip and block levels. You will collaborate with CAD and Technology teams for flow bring up and validation while working with implementation teams to drive signoff closure for tapeout. Additionally, you will manage schedules, support cross-functional engineering efforts, and work on padring, bump, and RDL design alongside package and floorplan teams. Required skills include experience with DRC/LVS/ANT flows, RTL to GDS physical design flow knowledge, scripting for debugging, and proficiency in industry standard tools like Mentor Calibre or Synopsys ICV.