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CMOS Photolithography Etching Deposition Chemical Mechanical Polishing Flip-Chip Wafer-Level Packaging Fan-Out Wire Bonding Molding System-in-Package Automated Test Equipment Scan and Built-In Self-Test Burn-In Design Failure Mode and Effects Analysis First Article Inspection Minitab Six Sigma Lean Methodologies +14 more Show less

RTL2GDSII EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows +4 more Show less

EDA RTL2GDSII ASIC SOC CMOS DFT Scan MBIST LBIST Standard Cells Physical Design Flows +6 more Show less

RTL2GDSII EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows +4 more Show less

Lumerical COMSOL HFSS Spectre ADS Python PostgreSQL Kubernetes Terraform AWS Docker CI/CD Prometheus Grafana +9 more Show less

Python EDA tools HDL simulators HDL Lint tools AXI AHB RF Verification Mentor Graphics Calibre RISC-V +4 more Show less

Python EDA tools HDL simulators HDL Lint tools AXI AHB +1 more Show less

Python EDA tools HDL simulators HDL Lint tools AXI AHB +1 more Show less

Python EDA tools HDL simulators HDL Lint tools AXI AHB +1 more Show less

C C++ Python RF communication systems FPGA Embedded firmware Hardware development Automation software Modular software design Low-level silicon control HIL testing CI/CD +7 more Show less

RF Analog IC Design Verilog Cadence Virtuoso Calibre Python MATLAB HFSS ADS Linux Git JIRA Confluence Agile Methodology ITAR Compliance +10 more Show less

Verilog System Verilog AXI AHB RTL Multicore CPU subsystem design Embedded processors Clock domain crossings Power optimization High speed design techniques Low power design techniques RFIC design ASIC development Micro-architecture definition Simulation and modeling RF/analog/mixed-signal circuits Lab measurement and characterization Production testing Qualification processes +14 more Show less

Cadence APD+/SIP SIWave HFSS ADS BGA Co-packaged Optics (CPO) Signal Integrity (SI) Power Integrity (PI) EM simulation Package design electrical review Substrate design RF Digital High-speed and mixed signal die Package/SIP layout +10 more Show less

Cadence APD+/SIP SIWave HFSS ADS BGA Co-packaged Optics (CPO) Signal Integrity (SI) Power Integrity (PI) EM Simulation Package Design Electrical Review Substrate Design RFIC ASIC Manufacturing Reviews +9 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 Teradyne Advantest Streaming_Scan_Network ATPG SDF_annotated_gate_level_simulations In-System_Test(IST) boundary_scan(IEEE_1149.1) +9 more Show less

Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 In-System_Test_(IST) boundary_scan_IEEE_1149_1 Automated_Test_Equipment_(ATE) Teradyne Advantest Streaming_Scan_Network cell-aware_fault_models_ATPG +9 more Show less

Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 Teradyne Advantest Streaming_Scan_Network ATPG SDF_annotated_gate_level_simulations In-System_Test boundary_scan functional_testing board_level_diagnostics +11 more Show less