Sr. RTL Design Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Austin, TX
Posted: today

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How this pay compares to similar roles

Similar $181k

$144k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $154,525–$208,225.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. RTL Design Engineer (Silicon Engineering)

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Senior RTL Implementation Engineer position available in Austin, TX for a leading semiconductor company focusing on advanced ASIC/SoC system integration. This role involves providing timing constraints for IPs and supporting physical implementation teams through synthesis, timing closure, and formality checks. The ideal candidate will have 5+ years of experience with embedded CPU subsystems and familiarity with AXI, AHB protocols. Proficiency in scripting languages like Python and expertise with EDA tools such as HDL simulators and linting utilities are essential. This role requires a deep understanding of the intricacies involved in high-scale semiconductor design and adherence to ITAR regulations for U.S. Department of State compliance.

Skills

Python EDA tools HDL simulators HDL Lint tools AXI AHB

What you'll do

Provide timing constraints for IPs during design phase.
Support physical implementation team in synthesis and timing closure processes.
Conduct formality checks to ensure design integrity and compliance.
Utilize EDA tools for HDL simulation and linting to validate designs.
Work with embedded CPU subsystems, including AXI and AHB protocols.

What we're looking for

5+ years of experience in RTL implementation
Experience with ASIC/SoC system integration and embedded CPU subsystems
Proficiency in scripting languages (e.g., Python)
Expertise with EDA tools including HDL simulators and linting tools
Knowledge of bus protocols such as AXI, AHB

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