Senior IC Package Design Engineer

SpaceX

Confirmed live yesterday Low trust

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Work type
On-site
Location
Austin, TX
Posted
113 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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How this pay compares to similar roles

Similar $195k
$146k most similar roles pay here $240k

This listing doesn't post a salary. Most similar roles pay $167,475–$222,425.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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TL;DR · Senior IC Package Design Engineer

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Sr. IC Package Design Engineer (Silicon Engineering) joins the Silicon Engineering team to develop next-generation ASICs for space and ground infrastructure. This role involves leading packaging for custom in-house ASICs and RFICs used in digital beam formers and modems. The engineer will own advanced package selection, BGA configuration, and package structure while managing layout, optimization, design verification, and tapeout. Key responsibilities include coordinating with cross-functional teams to analyze trade-offs, optimizing silicon floor plans, and performing signal/power integrity and RF performance simulations. Required skills include experience with IC package design, substrate design for high-speed and mixed-signal dies, and proficiency in tools like Cadence APD+/SIP, SIWave, HFSS, and ADS. The role addresses the technical challenge of providing reliable connectivity through advanced hardware components designed to operate in demanding orbital and terrestrial environments.

Skills

IC Package Design ASIC RFIC BGA SIP Power Integrity EM Simulation Cadence APD+ SIWave HFSS ADS Co-packaged Optics Substrate Design Tapeout Mixed Signal

What you'll do

  • Own and drive advanced package selection, BGA configurations, and package structures for custom ASICs and RFICs.
  • Execute package and SIP layout, optimization, design verification, and tapeout processes.
  • Coordinate with cross-functional teams to perform feasibility analysis and manage trade-offs for silicon floor plans.
  • Optimize bump layouts and package pinouts based on system constraints.
  • Simulate and optimize signal integrity, power integrity, and RF performance of the package design.
  • Drive methodology improvements and innovations to increase productivity in the package design workflow.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience with IC package design.
  • Experience with Co-packaged Optics (CPO).
  • Thorough understanding of signal and power integrity fundamentals.
  • Substrate design experience for RF, digital, high-speed, and mixed-signal die.
  • Proficiency in Cadence APD+/SIP or similar design tools.
  • Fluency in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee to meet ITAR requirements.

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