Sr. RTL Design Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $160,000–$225,000 / yr
Posted: today

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k

This role $192k

$144k most similar roles pay here $234k

This role pays more than 60% of similar roles. Most pay $154,525–$208,225 — the shaded band above. At the midpoint, this role pays about $192k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. RTL Design Engineer (Silicon Engineering)

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This senior-level position in Redmond, WA is for an experienced ASIC Design Engineer to join a dedicated hardware design team. The role involves providing timing constraints for IPs and supporting the physical implementation team with synthesis, timing closure, and formality checks. Daily tasks include working on embedded CPU subsystems using AXI, AHB protocols, and scripting languages like Python. Candidates should have extensive experience in RTL implementation and familiarity with EDA tools such as HDL simulators and linting utilities. The ideal candidate will contribute to the development of complex SoC systems at a large scale, addressing intricate timing and integration challenges within a high-stakes environment.

Skills

Python EDA tools HDL simulators HDL Lint tools AXI AHB

What you'll do

Provide timing constraints for IPs during the design process.
Support physical implementation teams with synthesis and timing closure tasks.
Conduct formality checks to ensure design integrity and compliance.
Utilize EDA tools such as HDL simulators and linting tools effectively.
Script automation solutions using Python or similar languages.

What we're looking for

5+ years of experience in RTL implementation
Experience with ASIC/SoC system integration and embedded CPU subsystems
Proficiency in scripting languages such as Python
Expertise with EDA tools including HDL simulators and linting tools
Knowledge of bus protocols like AXI, AHB

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