Senior RTL Design Engineer, Silicon Engineering

SpaceX

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$175,000–$280,000 / yr
Posted
113 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $228k
$140k most similar roles pay here $295k

This role pays more than 79% of similar roles. Most pay $172,000–$225,712 — the shaded band above. At the midpoint, this role pays about $228k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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View all roles at SpaceX

At a glance

TL;DR · Senior RTL Design Engineer, Silicon Engineering

Role Posting Log in to save

Sr. RTL Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for deployment in space and ground infrastructures. This role involves evaluating architectural trade-offs based on performance requirements, defining micro-architecture, and implementing RTL in Verilog and System Verilog. The engineer will integrate designs into the top level, provide timing constraints, support physical implementation through synthesis and timing closure, and participate in silicon bring-up and validation. Key technical skills include experience with ASIC/SoC system integration, embedded CPU subsystems, standard bus protocols like AXI and AHB, and high speed and low power design techniques. The candidate should be proficient in Python scripting and familiar with EDA tools such as HDL simulators and lint tools to solve complex problems involving clock domain crossings and power optimization for the Starlink network.

Skills

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB HDL Simulators EDA Tools Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up

What you'll do

  • Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
  • Define micro-architecture for next-generation ASICs used in space and ground infrastructure.
  • Implement RTL designs using Verilog or System Verilog.
  • Integrate designs into the top level to deliver synthesis and timing clean results.
  • Collaborate with verification teams to ensure all design aspects are fully covered and verified.
  • Provide timing constraints for IPs and support physical implementation tasks like synthesis and timing closure.
  • Participate in silicon bring-up and validation processes.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in RTL implementation.
  • Ability to solve complex problems including clock domain crossings and power optimization.
  • Experience with ASIC/SoC system integration and embedded CPU subsystems.
  • Experience with standard bus protocols such as AXI and AHB.
  • Proficiency in high speed and low power design techniques.
  • Scripting skills in languages like Python and experience with EDA tools.
  • Must meet U.S. Government export control requirements (ITAR).

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