Sr. RTL Design Engineer (Silicon Engineering)

SpaceX

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $170,000–$235,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $181k

This role $202k

$142k most similar roles pay here $245k

This role pays more than 68% of similar roles. Most pay $154,525–$208,225 — the shaded band above. At the midpoint, this role pays about $202k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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View all roles at SpaceX

At a glance

TL;DR · Sr. RTL Design Engineer (Silicon Engineering)

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This senior-level position in Sunnyvale, CA is for an experienced ASIC design engineer to join a dynamic semiconductor team. The role involves providing timing constraints for IPs and supporting the physical implementation team with synthesis, timing closure, and formality checks. Daily tasks include working on embedded CPU subsystems using AXI and AHB protocols, scripting with Python, and utilizing EDA tools such as HDL simulators and linting utilities. Ideal candidates have over five years of RTL implementation experience and a strong background in ASIC/SoC system integration. The role requires expertise in semiconductor design at scale, addressing complex timing and verification challenges within the constraints of ITAR regulations.

Skills

Python EDA tools HDL simulators HDL Lint tools AXI AHB

What you'll do

Provide timing constraints for IPs during the design phase.
Support physical implementation teams in synthesis and timing closure processes.
Conduct formality checks to ensure design integrity and compliance.
Utilize EDA tools such as HDL simulators and lint tools effectively.
Script automation tasks using Python or other scripting languages.

What we're looking for

5+ years of experience in RTL implementation
Experience with ASIC/SoC system integration and embedded CPU subsystems
Proficiency in scripting languages like Python
Expertise with EDA tools including HDL simulators and linting tools
Knowledge of bus protocols such as AXI, AHB

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