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Digital Forensics Incident Response DFIR Threat Hunting Malware Analysis Memory Forensics EDR AWS Azure GCP Python PowerShell Bash Active Directory Volatility X-Ways FTK EnCase Autopsy Linux Windows MacOS OT ICS Reverse Engineering Sandboxing +21 more Show less

Physics-Informed Machine Learning Python PyTorch JAX C/C++ Matlab Azure Kubernetes Service (AKS) Google Distributed Cloud Edge (GDCE) Apache Spark Azure Databricks MLflow Data Pipelines Deep Learning Optimization Data Management +10 more Show less

SystemVerilog UVM ASIC FPGA Verilog Python TCL Linux Questa Modelsim Formal Verification AXI PCIe DSP GitLab Constrained Random Testing Assertions Register Abstraction Layer Xilinx +14 more Show less

SystemVerilog UVM ASIC FPGA Verilog Python TCL Linux Questa ModelSim Formal Verification AXI PCIe DSP GitLab VHDL Constrained Random Testing Assertions Register Abstraction Layer +14 more Show less

ASIC FPGA SystemVerilog Verilog UVM OVM SVA Digital Signal Processing Formal Verification Constrained Random Testing Functional Coverage Synthesis Place and Route Agile Microsoft Office +10 more Show less

ASIC SoC RTL GDS2 FPGA SerDes DSP SPI I2C APB AXI Ethernet DFT Synthesis Timing Closure Low-Power Design Scripting +12 more Show less

ASIC SoC Physical Design RTL-to-GDSII Floorplanning STA IR/EM PV TCL Python Shell PnR CTS MMMC ECO SDC Mixed-Signal DFT +13 more Show less

Physical Design RTL-to-GDS SerDes PHY Logic Synthesis Place and Route Clock Tree Synthesis Physical Verification Static Timing Analysis Verilog Floorplanning IP Integration Logic Equivalence Checking Power Gating Scan Stitching EDA Tools Circuit Simulation Logic Simulation +12 more Show less

Physical Design CAD Tools Tcl Python Perl PNR STA RC Extraction EMIR ML GenAI SoC Design Signoff Physical Verification +9 more Show less

Reinforcement Learning Imitation Learning Python PyTorch C++ CUDA JAX Kubernetes Ray Slurm Isaac Lab Isaac Sim Omniverse MuJoCo Brax PPO SAC GRPO RLHF DPO Sim-to-Real CI/CD Digital Twins Edge Computing MPC Trajectory Optimization ISO 26262 SOTIF ISO 13849 Bazel +25 more Show less

Solidworks Ansys Icepack Ansys Mechanical Python Excel Allegro Thermal Management PCB Design Simulations Profilometry Keyence ATE Test Hardware Mechanical Prototyping +8 more Show less

ASIC Physical Verification DRC LVS ERC PERC DFM ICV Calibre Pegasus Python Tcl Perl Floorplan Tape-out 3nm 2nm 2.5D 3D Chiplet EDA Tools +15 more Show less

ASIC Design SystemVerilog Verilog HDL UVM RTL Design FPGA Static Timing Analysis (STA) Logic Synthesis Lint CDC IP Integration PPA Machine Learning LLM Acceleration NPU TCP/IP Ethernet Altera AMD Xilinx +14 more Show less

Java Spring Boot Python Cobol REST APIs Microservices Kafka MongoDB Git Jenkins Maven Gradle npm Artifactory OAuth OpenID SAML OWASP Swagger OpenAPI Agile Distributed Systems +17 more Show less

X-ray Imaging Systems Metrology Physics System Requirements Feasibility Studies Product Risk Management Inspection Systems +2 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis +12 more Show less

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification +9 more Show less

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification +9 more Show less

ASIC FPGA Verilog VHDL SystemVerilog Python Tcl Perl Vivado Libero ISE Synplify QuestaSim UVM OVM SVA Digital Design Synthesis Place and Route Timing Closure Clock-Domain-Crossing Logic Analyzer Oscilloscope +18 more Show less

VHDL ASIC Design FPGA Design FPGA-to-ASIC Conversion Vivado Libero Mentor Cadence Xilinx Microsemi JTAG Oscilloscope Logic Analyzer Synthesis Place and Route Power Utilization System Simulation +12 more Show less