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SystemVerilog UVM VCS GDB RISCV C Assertion-based Verification Functional Coverage Random Stimulus Firmware ASIC Verification Memory Subsystem High Speed IO Object Oriented Programming +9 more Show less

Physical Design Floorplanning Synthesis Placement Routing Clock Tree Synthesis Static Timing Analysis Physical Verification Formal Equivalence Power Optimization IR-drop Electromigration EDA Tools Low Power Verification +9 more Show less

Physical Design Place and Route Static Timing Analysis Physical Verification Formal Equivalency Verification IR-Drop Electromigration TCL Python Synopsys Fusion Compiler PrimeClosure Primetime Formality VCLP Star-RC Redhawk SC Cadence Innovus Siemens Calibre ASIC SOC +15 more Show less

RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII +14 more Show less

CFD STAR-CCM+ Fluent Python MATLAB NASA CEA Cantera CHEMKIN Fluid Dynamics Aerothermodynamics Scripting Automation Java Macros UDFs +9 more Show less

Site Reliability Engineering DevSecOps Microsoft Azure Windows Linux SQL Server PowerShell Relativity Nuix Confluence Microsoft 365 SharePoint ITIL Automation Vulnerability Remediation Application Monitoring +11 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting SoC Circuit Design +5 more Show less

Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design +8 more Show less

ASIC RTL to GDS Flow Virtuoso Circuit Design Synthesis Place and Route System Simulation Design Verification Scripting +4 more Show less

CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Computer Architecture Physical Design +12 more Show less

ASIC RTL to GDS Flow Virtuoso Synthesis Place and Route System Simulation Scripting Verification IC Package Logic Design +5 more Show less

DFT JTAG SCAN BIST RTL ASIC FinFET Synopsys Design Compiler Tetramax Spyglass VCS ATE Python SQL JMP Statistical Process Control ISO 9001 Root Cause Analysis +14 more Show less

System Verilog UVM ASIC Verification Python Perl C C++ Emulation Formal Verification SoC Architecture Silicon Bring-up Post-Silicon Debug +7 more Show less

Verilog System Verilog DFT ATPG RTL Design UVM OVM Python Tcl Perl Shell Synopsys DC Compiler PrimeTime Cadence Virtuoso VCS Static Timing Analysis FPGA HBM PCIe SerDes +15 more Show less

ASIC System Verilog UVM Veloce Palladium Zebu HAPS C C++ Python Perl Linux Networking Post-silicon Lab Bring-up Verification Methodology Silicon One +11 more Show less

PET/CT PET/MR Nuclear Medicine Medical Imaging Physics Image Reconstruction Signal Processing Scientific Computing Data Analysis Image Processing Systems Engineering Firmware Hardware Software Development Numerical Methods +9 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Scripting Verification Validation +4 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Power Optimization Fuse Controller Verification Synthesis +10 more Show less

Static Timing Analysis STA Synthesis ECO RTL Floor-planning DFT Python Tcl Make Synopsys PrimeTime Cadence Tempus Physical Design +8 more Show less

Physical Verification DRC LVS ERC Antenna ESD SVRF Calibre Python TCL Perl PDK CAD AI Automation Silicon Design +11 more Show less