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UVM SystemVerilog Verilog Python C/C++ VCS Verdi GDB HLS DisplayPort HDMI MIPI DSI Functional Coverage Assertion-Based Verification Constrained-Random Stimulus Version Control +11 more Show less

SystemVerilog UVM ASIC Verification Python Perl RTL VCS dc_shell GDB Debussy Object-Oriented Programming Design Automation Pre-silicon Verification Coverage-based Verification +9 more Show less

System Verilog UVM Python Verilog RTL VCS Verdi OOPS ASIC Verification Computer Architecture Functional Coverage Scripting +7 more Show less

ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP +15 more Show less

Verilog SystemVerilog Python Perl RTL ASIC Mixed-Signal Design DFT Logic Design Waveform Debug PLL High-Speed Interconnects Simulation Hardware Design Digital Design +10 more Show less

UVM System Verilog Python Shell Pearl Git ASIC FPGA IP Verification Silicon Chip Architecture Performance Instrumentation +6 more Show less

SystemVerilog UVM Constrained-Random Verification Coverage-Driven Verification Python Perl Shell ASIC Verification RTL CHI AXI FPGA Emulation Coherent Interconnects +9 more Show less

UVM C C++ ASIC SoC Pre-Silicon Verification Post-Silicon Validation FPGA Simulation Emulation Coverage Closure Jasper Formal Verification Testbench Development Silicon Bring-up Firmware Computer Architecture +12 more Show less

RTL Verification Mixed-Signal Simulation Python Verilog SPICE PCB Design Analog Simulation SOC Mixed-Signal Simulation PrimeSim System Validation Pre-silicon Verification ASIC FPGA System Design Flows +9 more Show less

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC RTL Python C C++ Perl Shell Git Subversion QuestaSim Synplify Quartus Vivado Unix Linux Computer Vision +17 more Show less

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC RTL Python C C++ Perl Shell Git Subversion QuestaSim Synplify Quartus Vivado Unix Linux Computer Vision DFT +18 more Show less

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC Python C C++ Perl Unix Linux Git Subversion QuestaSim Synplify Quartus Vivado Constrained-Random Testing Assertion-Based Verification +16 more Show less

RTL Verification Verilog Python Simulation HSPICE PrimeSim PCB Design ASIC FPGA System Validation Pre-silicon Verification System Design Flows +7 more Show less

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects Coherency Simulation Test Bench IP Verification Post-processing +9 more Show less

Physical Verification DRC LVS ERC Antenna ESD Calibre TCL Python Perl SVRF PERC PDK CAD Methodology Flow Automation shift left PV +11 more Show less

CPU Performance Modeling Performance Correlation micro architecture Python C++ Perl ARM A64 x86 Workload Analysis Performance Verification CPU Design Scripting Performance Analysis +8 more Show less

System Verilog UVM VCS Verdi Indago GDB C/C++ Perl Assertion-Based Verification Functional Coverage Random Stimulus ASIC Verification Post-silicon Verification +8 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification Constrained-Random Testing Coverage-Driven Verification RTL Computer Architecture Hardware Modeling Emulation Performance Profiling Formal Verification +9 more Show less

GPU Architecture C++ Python Linux RTL Emulation SystemC OpenGL Vulkan OpenCL Performance Modeling SoC AI/ML Profiling Tools Workload Characterization +10 more Show less

system Verilog UVM FPGA RTL RDMA SDN Agile Azure Network Protocols +4 more Show less