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UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI Simulation +5 more Show less

PCIe UVM System Verilog Python CHI AXI Simulation Generative AI Coverage Signoff +4 more Show less

FPGA VHDL System Verilog UVM OSVVM Quartus Modelsim Questa Sim Python MATLAB Simulink JIRA GIT DSP RTL ASIC LabVIEW AXI Avalon NIOS +15 more Show less

SystemVerilog UVM VCS GDB RISCV C Assertion-based Verification Functional Coverage Random Stimulus Firmware ASIC Verification Memory Subsystem High Speed IO Object Oriented Programming +9 more Show less

UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

System Verilog UVM VCS C C++ Python Perl Shell ASIC Verification RTL FPGA Debussy GDB DDR LPDDR +10 more Show less

Physical Verification DRC LVS ERC Antenna ESD SVRF Calibre Python TCL Perl PDK CAD AI Automation Silicon Design +11 more Show less

Go Distributed Systems CI/CD AWS Kubernetes GitHub Policy-as-Code Developer Infrastructure Observability AI-assisted Development source-control integration +6 more Show less

SystemVerilog UVM SVA FPGA SoC Xilinx Python Tcl Makefile Git Linux CI/CD Ethernet PCIe JESD204C MIL-STD-1553 SPI Questa VCS Xcelium Vivado +16 more Show less

SystemVerilog UVM C C++ Python Perl ASIC Verification Constrained Random Testing Assertion-based Verification VCS IES GDB Debussy Memory Management Computer Architecture Functional Coverage Scoreboards +12 more Show less

UVM SystemVerilog Verilog Python C++ HLS VCS Verdi GDB DisplayPort HDMI MIPI DSI Assertion-based Verification Functional Coverage Constrained-random Version Control +11 more Show less

SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Scripting Design Automation Functional Coverage +10 more Show less

System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Coverage Metrics Logic Design ASIC Verification DFT IST Object-Oriented Programming Automation +9 more Show less

System Verilog UVM RTL Verilog Python VCS Verdi Computer Architecture Functional Coverage Scripting ASIC Verification Simulation Tools +7 more Show less

Verilog SystemVerilog Python Perl RTL ASIC Mixed-Signal Design DFT Waveform Debug Circuit Design Digital Design Logic Design PLL High-Speed Interconnects Simulation Verification +11 more Show less

C C++ SystemVerilog Python Perl Ruby FPGA HAPS Xilinx JTAG Logic Analyzers Oscilloscopes UART AMBA AXI AHB APB SPI I2C I3C USB Assembly Linker Scripts Makefile +19 more Show less

SystemVerilog C++ Python GPU Architecture RTL Constrained-Random Testing Functional Coverage Computer Architecture Graphics Pipelines 3D Graphics Verification Testbenches Semiconductor Design +7 more Show less

ASIC Verification UVM System Verilog C++ Object-Oriented Programming SoC Architecture CPU Verification RTL FPGA Emulation +5 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling Coherent Interconnects +9 more Show less

Java JavaScript TypeScript Apache Kafka Kafka Streams Apache Flink Spark Streaming Redis Elasticsearch Kibana Logstash Docker Kubernetes OpenTelemetry Grafana LangChain LLM Microservices Data Visualization +14 more Show less