Senior FPGA Verification Engineer

Anduril Industries

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Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$191,000–$254,000 / yr
Posted
11 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $190k
This role $222k
$129k $267k
below market most similar roles pay here above market

This role pays more than 83% of similar roles. Most pay $166,538–$214,000 — the blue band above. At the midpoint, this role pays about $222k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 901 open roles on FindRole.

Listed pay typically runs $166,000–$220,000 across 858 roles with salary data.

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At a glance

TL;DR · Senior FPGA Verification Engineer

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The Senior FPGA Verification Engineer joins the Imaging team to support the development of new product lines. In this role, you will work with an interdisciplinary technical team to define designs, build prototypes for ground and flight testing, and mature those prototypes into final products. Your daily responsibilities include designing verification environment architectures, creating written test plans, and developing testbenches for RTL blocks. You will utilize SystemVerilog, OVM/UVM, VHDL, and Verilog, while employing methodologies like constrained-random testing and functional coverage analysis. You will also use tools such as QuestaSim, Synplify, Quartus, and Vivado within Unix/Linux environments. This position focuses on developing state-of-the-art imaging systems that utilize computer vision, perception, electro-optical, infrared, and sensor data to provide a tactical advantage.

Skills

SystemVerilog VHDL Verilog UVM OVM FPGA ASIC Python C C++ Perl Unix Linux Git Subversion QuestaSim Synplify Quartus Vivado Constrained-Random Testing Assertion-Based Verification

What you'll do

  • Design and architect verification environments using SystemVerilog or OVM/UVM.
  • Create written test plans, test cases, and track code and functional coverage.
  • Develop testbenches for the verification of RTL blocks using VHDL or SystemVerilog.
  • Recommend new tools and practices to improve the ASIC and FPGA verification flow.
  • Contribute to engineering estimates for new program pursuits.
  • Provide technical leadership by breaking down work, planning activities, and reporting status.

What we're looking for

  • A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
  • 8+ years of experience developing HDL firmware for FPGA devices.
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
  • Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification.
  • Experience using revision control systems such as Git or Subversion to manage source code and maintain configuration integrity.
  • Eligible to obtain and maintain an active U.S. Secret security clearance.
  • Experience with ASIC/FPGA lab validation, debug, DFT, and production test concepts (preferred); proficiency with Unix/Linux, scripting (C, C++, Python, Perl, or shell), and industry-standard tools (preferred).

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