Senior FPGA Verification Engineer

What you'll do

• Design and architect verification environments using SystemVerilog or OVM/UVM.
• Create written test plans, test cases, and track code and functional coverage.
• Develop testbenches for the verification of RTL blocks using VHDL or SystemVerilog.
• Recommend new tools and practices to improve the ASIC/FPGA verification flow.
• Provide engineering estimates for new program pursuits.
• Provide technical leadership by breaking down work, planning activities, and reporting status.

What we're looking for

• A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
• 8+ years of experience developing HDL firmware for FPGA devices.
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification.
• Experience using revision control systems such as Git or Subversion to manage source code and maintain configuration integrity.
• Eligible to obtain and maintain an active U.S. Secret security clearance.
• Experience with ASIC/FPGA lab validation, debug, DFT, and production test concepts (preferred); proficiency with Unix/Linux, scripting, and industry-standard simulation tools (preferred).