Senior Cell Modeling and Verification Engineer

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 6 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k

This role $177k

$125k $241k

below market most similar roles pay here above market

This role pays less than 58% of similar roles. Most pay $177,050–$222,000 — the blue band above. At the midpoint, this role pays about $177k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Cell Modeling and Verification Engineer

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The Senior Cell Modeling and Verification Engineer joins the NVIDIA VLSI team to develop groundbreaking ASIC products. This role sits at the intersection of circuit and digital design, focusing on crafting power-efficient and performance-leading SoCs and GPUs. The engineer will develop behavioral models and verification for custom mixed-signal design cells used across all products. Day-to-day responsibilities include modeling, verifying, emulating, and prototyping mixed-signal designs while collaborating with cross-functional teams on library builds, cell integration, ASIC verification, and DFT simulation. Key requirements include proficiency in Verilog HDL, SystemVerilog, Perl, and Python. Candidates must possess a strong understanding of PLLs, high-speed interconnects, and fundamental digital logic design concepts. The position requires delivering fully verified, high-performance RTL to meet specific design, feature, and quality objectives for advanced hardware.

Skills

Verilog SystemVerilog Python Perl RTL ASIC Mixed-Signal Design DFT Logic Design Waveform Debug PLL High-Speed Interconnects Simulation Hardware Design Digital Design

What you'll do

Develop behavioral models and verification for custom mixed-signal design cells.
Use Verilog, SystemVerilog, Perl, or Python to model and verify mixed-signal designs.
Model and verify high-speed interconnects and PLL components.
Implement and deliver fully verified, high-performance RTL to meet design targets.
Perform RTL simulation and waveform debugging for ASIC products.
Coordinate with cross-functional teams on library builds, cell integration, and DFT simulation.
Document and deliver technical specifications for high-performance SoC and GPU designs.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience).
3+ years of relevant experience.
Hands-on experience with RTL simulation and waveform debug.
Strong understanding of Verilog HDL.
Scripting experience and skills using Python or Perl.
Knowledge of fundamental digital design and logic design concepts.
Previous digital design experience (preferred).
Previous experience running simulations in Verilog (preferred).