Senior Cell Modeling and Verification Engineer

Nvidia

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Posted
9 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k
This role $177k
$126k most similar roles pay here $233k

This role pays less than 51% of similar roles. Most pay $167,375–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Cell Modeling and Verification Engineer

The Senior Cell Modeling and Verification Engineer joins the VLSI team to develop groundbreaking ASIC products at the intersection of circuit and digital design. This role focuses on creating high-performance, power-efficient SoCs and GPUs by developing behavioral models and verification for custom mixed-signal design cells used across all company products. Day-to-day responsibilities include collaborating with cross-functional teams on library builds, cell integration, ASIC verification, and DFT simulation to deliver fully verified RTL that meets specific design targets. The successful candidate will utilize Verilog, SystemVerilog, Perl, and Python to model, verify, emulate, and prototype mixed-signal designs involving PLLs and high-speed interconnects. Required expertise includes RTL simulation, waveform debug, and a strong understanding of Verilog HDL along with fundamental digital and logic design concepts to solve complex hardware challenges in the visual and AI computing space.

What you'll do

  • Develop behavioral models and verification for custom mixed-signal design cells.
  • Model and verify high-speed interconnects and PLL designs using Verilog and SystemVerilog.
  • Perform RTL simulation and waveform debugging to ensure design quality.
  • Use Python or Perl scripts to automate modeling and verification tasks.
  • Deliver fully verified, high-performance RTL to meet specific design targets.
  • Coordinate with cross-functional teams on library build, cell integration, and DFT simulation.

What we're looking for

  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 3+ years of relevant experience in hardware design and methodologies.
  • Hands-on experience with RTL simulation and waveform debug.
  • Strong understanding of Verilog HDL.
  • Scripting skills using Python or Perl.
  • Knowledge of fundamental digital design and logic design concepts.
  • Understanding of PLL and other high-speed interconnects to model mixed-signal designs.

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