Browse tech roles

UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI Simulation +5 more Show less

PCIe UVM System Verilog Python CHI AXI Simulation Generative AI Coverage Signoff +4 more Show less

FPGA VHDL System Verilog UVM OSVVM Quartus Modelsim Questa Sim Python MATLAB Simulink JIRA GIT DSP RTL ASIC LabVIEW AXI Avalon NIOS +15 more Show less

UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

C C++ SystemVerilog Python Perl Ruby FPGA HAPS Xilinx JTAG Logic Analyzers Oscilloscopes UART AMBA AXI AHB APB SPI I2C I3C USB Assembly Linker Scripts Makefile +19 more Show less

SystemVerilog C++ Python GPU Architecture RTL Constrained-Random Testing Functional Coverage Computer Architecture Graphics Pipelines 3D Graphics Verification Testbenches Semiconductor Design +7 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling Coherent Interconnects +9 more Show less

SystemVerilog UVM Verilog VHDL Python C++ Perl Formal Verification UPF AMBA AXI AHB APB RTL Object-Oriented Programming Scripting Automation +12 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

System Verilog UVM SVA Verilog VCS Questa Perl Tcl Make files Gate Level Simulation Formal Equivalence LLMs Agentic AI Frameworks Mixed Signal Design Functional Coverage Co-simulation +11 more Show less

Quantum Computing SoC RTL Netlist Analog Mixed-Signal Design Verification DFT Python C C++ MATLAB Visual Studio Code AI Simulation Characterization Scripting High-Performance Computing +12 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification Pre-silicon Testbench Development Computer Architecture Arbitration Scripting Data Structures Algorithms RTL Performance Verification +10 more Show less

SystemVerilog UVM VMM SerDes PCI Express USB SATA Python Perl C/C++ Assertion-based Verification Functional Coverage coverage driven verification Mixed-signal Design Simulation Debug +11 more Show less

UVM System Verilog C++ Python Perl RTL SoC FPGA Emulation AI Accelerators Computer Architecture Interconnect Networks Simulation +8 more Show less