This role pays less than
91%
of similar roles. Most pay
$168,500–$216,062
— the shaded band above.
At the midpoint, this role pays about
$143k
versus about
$192k
for comparable roles.
Based on 240 similar postings.
Employer
About Broadcom
Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software
Broadcom currently has
119 open roles
on FindRole.
Listed pay typically runs
$121,900–$195,000
across 105 roles with salary data.
Senior Digital / Mixed-Signal IC Design or Verification Engineer will join the Mixed-Signal ASIC division to develop advanced semiconductor devices for data center enterprise storage. This role serves as a methodology leader and technical bridge between global teams, driving quality initiatives and pioneering automation including AI-assisted workflows. For design tasks, the engineer defines system requirements, performs Verilog coding, logic synthesis, formal verification, static timing analysis, and place and route while integrating digital cores with analog circuitry. Verification responsibilities include architecting UVM-based testbenches, managing coverage for tape-out projects, and utilizing SystemVerilog Assertions. Required skills include proficiency in EDA tools, Python, Perl, or TCL scripting, and a deep understanding of how digital logic interacts with analog boundaries. The role addresses the technical challenge of providing low-power, high-performance products for high-capacity storage needs across service providers.
Act as the primary technical liaison between local US teams and global cross-functional engineering organizations.
Translate complex specifications into actionable execution plans for mixed-signal ASIC products.
Provide technical support through all product development phases, including testing, yield analysis, and characterization.
Perform digital logic design, Verilog coding, synthesis, and static timing analysis for preamplifier products.
Architect and maintain advanced UVM-based testbenches for functional verification of complex mixed-signal ASICs.
Drive functional and code coverage to closure for major tape-out projects at both block and system levels.
Integrate modern automation and AI-assisted workflows to accelerate testbench generation and debug efficiency.
Develop scripts in Python, Perl, or TCL to automate verification workflows and manage regressions.
What we're looking for
Bachelor's degree in Engineering and 8+ years of related experience, or a Master's degree in Engineering and 6+ years of related experience.
Excellent spoken and written communication skills to coordinate technical problem-solving across global teams.
Proven ability to apply advanced math and physics to solve complex engineering problems.
Experience with ASIC EDA tools for synthesis, simulation, static timing analysis, formal verification, and place & route.
Deep familiarity with Verilog/VHDL RTL coding and logic design.
Expertise in coverage-driven verification processes and frameworks such as UVM or OVM.
Proficiency in scripting languages like Python, Perl, or TCL to automate workflows and manage regressions.
Understanding of silicon process technologies (CMOS and Bipolar) and device physics (preferred); expertise across both design and verification domains (preferred).
System Verilog
UVM
SVA
Verilog
VCS
Questa
Perl
Tcl
Make files
Gate Level Simulation
Formal Equivalence
LLMs
Agentic AI Frameworks
Mixed Signal Design
Functional Coverage
Co-simulation