below marketmost similar roles pay hereabove market
This role pays less than
57%
of similar roles. Most pay
$177,200–$216,887
— the blue band above.
At the midpoint, this role pays about
$177k
versus about
$197k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
694 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 651 roles with salary data.
The Senior Quantum Design Verification Engineer joins the Quantum 1st Party Hardware System-on-a-Chip team to advance the development of quantum System-on-a-Chip verification infrastructure. This role involves defining pre-silicon simulation and post-silicon validation plans for SoC and intellectual property. Key responsibilities include creating verification environments, developing testplans for digital and analog components, and performing Analog Mixed Signal Simulation models. The engineer will manage bug-tracking systems, coordinate with cross-functional teams, and drive continuous improvement of design verification processes. Required technical skills include proficiency in verification principles, testbenches, and stimulus generation, alongside experience with scripting languages like Python, Ruby, or Perl, and C/C++. The role addresses the technical challenge of scaling topological qubits and developing scalable, fault-tolerant quantum computing systems through hardware innovation.
Create and own verification environments and tests for IP and SoC level designs.
Validate designs in simulation using both pre- and post-layout Register Transfer Level (RTL) and netlists.
Define pre-silicon simulation verification plans for digital and analog components.
Perform Analog Mixed Signal Simulation models and silicon characterization of blocks.
Manage SoC/IP repositories, bug-tracking systems, and milestone reporting.
Coordinate with DFT teams to test specific Design for Test features.
Align verification methodologies with wider teams to drive continuous process improvement.
Automate simulation and data analysis environments using scripting languages like Python or MATLAB.
What we're looking for
Must have a Doctorate in Physics/Engineering with 1+ years of experience, a Master's with 4+ years, a Bachelor's with 6+ years, or equivalent experience.
Must be able to pass Microsoft Cloud Background Checks and meet export control regulations (ITAR/EAR/EU Dual Use).
Must provide proof of citizenship or U.S. permanent residency for export-controlled information access.
Degree in Electrical Engineering or related field (preferred).
6+ years of experience in design verification for complex SoC IPs and/or systems (preferred).
In-depth knowledge of verification principles, testbenches, stimulus generation, and chip/computer architecture (preferred).
Proficiency in scripting languages like Python, Ruby, or Perl, and experience writing tests in C and C++ (preferred).
Master's Degree in Physics, Engineering, or related field AND 4+ years.
FPGA
RTL
RF Design
Mixed Signal Electronics
Python
Tcl
Linux
Windows
Git
GitHub
Azure DevOps
CI/CD
SPI
USB
Serial
Scientific Computing
Quantum Computing
System Verilog
UVM
Verilog
SVA
VCS
Questa
Perl
Tcl
Make
Formal Equivalence
Gate Level Simulation
LLMs
Agentic AI
Functional Coverage
Mixed Signal Design
Co-simulation
ASIC Design Verification