Senior Quantum Design Verification Engineer

Microsoft

Quick summary

Work type
On-site
Location
Salary
$119,800–$234,700 / yr
Posted
22 days ago
Closes
Dec 2, 2026

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Competitive pay

How this pay compares to similar roles

Similar $196k
This role $177k
$106k most similar roles pay here $248k

This role pays more than 50% of similar roles. Most pay $176,412–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 622 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 559 roles with salary data.

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At a glance

TL;DR · Senior Quantum Design Verification Engineer

As a Senior Quantum Design Verification Engineer in Microsoft’s Quantum 1st Party Hardware System-on-a-Chip (SoC) team, you will lead the development of verification infrastructure for quantum SoCs, defining pre-silicon simulation and post-silicon validation plans. Your daily tasks include creating test environments, managing databases and bug-tracking systems, collaborating with cross-functional teams to ensure design integrity, and driving continuous improvement in verification methodologies. This role requires expertise in verification principles, scripting languages like Python or Perl, and experience with C/C++ for test writing. You will work on complex SoC designs, integrating analog and digital components, and leveraging AI-assisted solutions to enhance productivity. Join a team of leading experts shaping the future of quantum computing by solving intricate design challenges and advancing topological qubit technology.

What you'll do

  • Define and implement verification plans for both pre-silicon simulation and post-silicon validation of SoC/IP designs.
  • Set up and manage databases, bug-tracking systems, and coordinate milestone reviews for design verification projects.
  • Develop testbenches and simulations for digital and analog components in mixed-signal environments.
  • Collaborate with DFT team to ensure comprehensive testing of design-for-test features.
  • Align verification methodologies across teams and drive continuous improvement in verification processes.
  • Create and maintain simulation environments, including scripting and debugging designs using Python or MATLAB.

What we're looking for

  • 6+ years of experience in design verification with complex SoC IPs/systems.
  • Proven expertise in verification principles, testbenches, and stimulus generation.
  • Strong background in creating simulation environments and debugging designs.
  • Solid understanding of chip architecture and Analog/Digital interface verification.
  • Proficiency in scripting languages (Python, Ruby) and C/C++ for writing tests.
  • Experience with AI-assisted solutions and automation tools like MATLAB/Python.

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