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ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP +15 more Show less

UVM C C++ ASIC SoC Pre-Silicon Verification Post-Silicon Validation FPGA Simulation Emulation Coverage Closure Jasper Formal Verification Testbench Development Silicon Bring-up Firmware Computer Architecture +12 more Show less

System Verilog UVM Python PCIe CXL CHI AMBA Generative AI Fabric Interconnects Coherency Simulation Test Bench IP Verification Post-processing +9 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification Constrained-Random Testing Coverage-Driven Verification RTL Computer Architecture Hardware Modeling Emulation Performance Profiling Formal Verification +9 more Show less

system Verilog UVM FPGA RTL RDMA SDN Agile Azure Network Protocols +4 more Show less

VHDL System Verilog UVM OSVVM FPGA RTL Modelsim Quartus Mentor CDC Python MATLAB SimuLink GIT JIRA AXI Avalon NIOS DSP LabVIEW +14 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification RTL Computer Architecture Testbench Development Regression Triage Coverage Closure Debug Caches Coherency Pipelines Arbitration Interconnect Networks Algorithms Data Structures +14 more Show less

UVM System Verilog Python CHI AMBA AXI PCIe CXL Generative AI IP Verification random-stimulus Simulation Test Bench Protocol Bridges Power Management Virtualization +11 more Show less

SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS +10 more Show less

SystemVerilog UVM Verilog VHDL Python C++ C Perl Formal Verification UPF AMBA AXI AHB APB ASIC Design RTL Object-oriented programming Automation +13 more Show less

Mixed-Signal Verification UVM SystemVerilog Verilog VHDL SVA Static Timing Analysis Logic Synthesis Place and Route Formal Verification Python Perl TCL CMOS Bipolar EDA Tools +11 more Show less

ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis +10 more Show less

System Verilog UVM Verilog SVA VCS Questa Perl Tcl Make Formal Equivalence Gate Level Simulation LLMs Agentic AI Functional Coverage Mixed Signal Design Co-simulation ASIC Design Verification +12 more Show less

Quantum Computing SoC Design Verification RTL Netlists Analog Mixed-Signal DFT Python C C++ Ruby Perl Matlab Visual Studio Code Azure AI Simulation Validation Characterization +14 more Show less